| 卫星高速数传系统多码率融合LDPC编码器设计 |
| 葛广君, 殷柳国 |
| 清华大学 航天航空学院, 清华信息科学与技术国家实验室(筹), 北京 100084 |
| Multi-rate LDPC encoder for high-speed satellite data transmissions |
| GE Guangjun, YIN Liuguo |
| Tsinghua National Laboratory for Information Science and Technology, School of Aerospace Engineering, Tsinghua University, Beijing 100084, China |
摘要:
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| 摘要针对卫星高速数传系统的高增益、多码率、高可靠性通信编码应用需求, 提出了一种低密度奇偶校验(LDPC)码组的低实现复杂度、高速的编码器设计实现方案, 通过高效复用不同码率和不同扩展因子的编码硬件资源, 并采用低存储和局部三模冗余设计, 有效降低了多码率高速LDPC编码器的整体硬件规模并显著提升了编码速率和可靠性。现场可编程门阵列(FPGA)实现结果表明: 该方法设计的融合28种码字的航天加固编码器可基于单片Xilinx XC2V3000 FPGA芯片实现, 最高编码速率可达3.2 Gb/s; 其触发器、查找表和存储器资源与已有方案相比, 分别降低了24.5%、34.4%和11.1%。该编码器设计方案在当前及未来的卫星数传系统中具有较高应用价值。 | |||
| 关键词 ：低密度奇偶校验码,高速编码器设计,多码率融合,低复杂度,卫星数传 | |||
| Abstract：Satellite data transmission systems need high coding gains, multiple rates and high reliability channel coding. A low complexity, high speed encoder is designed for low-density parity-check (LDPC) codes, which reduces the hardware size and improves the encoding speed and reliability. The system reuses hardware resources for codes of various rates and lengths and uses a low-storage architecture and a partially triple-modular-redundant design scheme. Field programmable gate array (FPGA) synthesized results show that the encoder integrates 28 codes with aerospace reinforcement and a maximum encoding speed of 3.2 Gb/s in a Xilinx XC2V3000 FPGA chip. The flip-flop, look-up table (LUT) and RAM costs of the encoder are 24.5%, 34.4% and 11.1% less than that for the traditional scheme. This encoder design scheme will improve satellite data transmission systems. | |||
| Key words：low-density parity-check (LDPC) codeshigh-speed encoder designmulti-rate integratedlow-complexitysatellite data transmission | |||
| 收稿日期: 2015-12-02 出版日期: 2016-07-01 | |||
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| 通讯作者:殷柳国, 副研究员, E-mail: yinlg@tsinghua.edu.cnE-mail: yinlg@tsinghua.edu.cn | |||
| 引用本文: |
| 葛广君, 殷柳国. 卫星高速数传系统多码率融合LDPC编码器设计[J]. 清华大学学报（自然科学版）, 2016, 56(6): 656-660. GE Guangjun, YIN Liuguo. Multi-rate LDPC encoder for high-speed satellite data transmissions. Journal of Tsinghua University(Science and Technology), 2016, 56(6): 656-660. |
| 链接本文: |
| http://jst.tsinghuajournals.com/CN/10.16511/j.cnki.qhdxxb.2016.22.028或 http://jst.tsinghuajournals.com/CN/Y2016/V56/I6/656 |
图表:
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| 图１ AR４JA 码组编码器的设计 |
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| 图２ 不同码率编码矩阵结构 |
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| 图３ 可配置循环移位寄存器 |
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| 图４ 核内多路并行编码结构 |
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| 表１ 不同扩展因子码字的编码速率 |
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| 图５ 级联编码示意图 |
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| 表２ 不同码率下存储量对比 |
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| 图６ 各结构差错扩散示意图 |
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| 表３ 本文与文[７]方案硬件资源对比 |
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