Leibo Liu, Ph.D.

Tenured Professor (长聘教授)
Institute of Microelectronics,
Tsinghua University,Beijing, 100084, P. R. China
Office：+8, Email: liulb@tsinghua.edu.cn
Homepage:http://www.tsinghua-wx.cn/liulb



1999年和2004年分别在清华电子工程系和微电子所获得学士和博士学位。2004年留校任教, 2006年、2013年和2017年分别在欧洲微电子中心、美国麻省理工学院和英国牛津大学学术访问。现为清华微电子所长聘正教授(Tenured Prof.), 博士生导师, 同时担任清华大学硬件安全和密码芯片实验室主任、清华大学移动计算研究中心副主任。长期从事可重构计算及其芯片、硬件安全和密码芯片等关键技术研究。先后主持国家重点研发计划项目(总负责人)、863计划重点项目(首席专家)、国家自然科学基金重点项目(总负责人)、“核高基”重大专项课题(总负责人)、国防科工局基础研究项目、国际合作重大项目等20余个项目。发表SCI索引论文130余篇(IEEE/ACM Transactions/Journal论文76余篇)、EI索引论文80余篇(ISCA/DAC等顶级会议论文19余篇), 授权发明专利80余项, 出版著作5部、译作4部。历任亚洲固态电路会议IEEE A-SSCC的组委会主席/副主席、TPC副主席、TPC委员等；电子设计自动化领域顶级会议DAC的TPC委员；IEEE CAS VSPC的TC委员；IEEE电路与系统权威期刊《IEEE Circuits and Systems Magazine》的副总编辑；中国工程院刊 FITEE执行副主编；中国密码学会密码芯片专委会副主任委员、秘书长；ISO/IEC JTC1/SC27 国际标准注册专家。所突破的关键技术在信息安全芯片、可编程器件、可穿戴计算芯片和CPU芯片加速器等领域取得应用。获国家技术发明二等奖、中国专利金奖、教育部技术发明一等奖、江西省科技进步二等奖等科技奖励。
独立主持4门课程, 获清华大学本科生精品课、北京市青年教师教学竞赛一等奖、清华大学青年教师教学竞赛一等奖、清华大学青年教师教学优胜奖、MOOC教学先锋奖等多个教学奖励。
[EDUCATION]
September 1999
-July 2004
Ph.D.
Institute of Microelectronics, Tsinghua University, Beijing, China
Dissertation: JPEG2000 Still Image Compression and VLSI Implementation (Tsinghua Outstanding Doctoral Dissertation Award)
Supervisor: Professor Zhihua Wang and Professor Hongyi Chen

September 1994
- July 1999
B.Sc.
Department of Electronic Engineering, Tsinghua University, Beijing, China

[PROFESSIONAL CAREER]
December 2017
-Present
Tenured Professor
Institute of Microelectronics,
Tsinghua University, Beijing, China

January 2017-
November 2017
Tenured Associate Professor
Institute of Microelectronics,
Tsinghua University, Beijing, China

July 2017-
July 2017
Visiting Scholar
Department of Education,
University of Oxford, UK

February 2013-
October 2013
Visiting Scholar
Computer Science and Artificial Intelligence Laboratory (CSAIL), Massachusetts Institute of Technology (MIT), Cambridge, MA, USA

November 2007-
December 2016
Associate Professor
Institute of Microelectronics, Tsinghua University, Beijing, China

June 2006-
September 2006
Visiting Scholar
Interuniversity Microelectronics Center (IMEC), Belgium

August 2004-
October 2007
Assistant Professor
Institute of Microelectronics, Tsinghua University, Beijing, China

[CURRENT RESEARCH]
Reconfigurable Computing
1. computing principles, hardware/software architecture, programming paradigms and compiling techniques of reconfigurable computing Processor (RCP)

2. fault-tolerance and reliability of reconfigurable interconnection, reconfigurable network-on-chip

3. reconfigurable cryptographic processors and countermeasures against side-channel attacks

4. reconfigurable multimedia processor

Computer Vision
1. algorithm-hardware co-optimization for low level vision
2. algorithm optimization and VLSI accelerator design for 2D & 3D image based face alignment

Baseband Processor
massive MIMO Detection, low complexity - high parallelism detection algorithm, VLSI architecture for detector

[SELECTED RESEARCH GRANTS IN RECENT YEARS]
1
Funding Organization
National Key R&D Program of China

Program
Optoelectronics and microelectronic devices and integration

Title
Key Technologies of Dynamic Reconfigurable System Chips for Information Security

Principal Investigator
Self (Leibo Liu)

Co-Investigators
Prof. Wei Ge(Southeast University)
Prof. Zhihua Feng (Beijing Institute of Computer Technology and Applications)
Prof. Ziyuan Zhu (Institute of Information Engineering, Chinese Academy of Sciences)

Period Held
2019-2023

Level of Support
Total cash

Total Cash
US$3,650,000 (i.e. 26,100,000RMB)

Note: National Key R&D Program of China is a combination of the original National Key Basic Research and Development Program (973 Program), the National High Technology Research and Development Program (863 Program), and many projects.


2
Funding Organization
National Natural Science Foundation of China (NSFC)

Program
Key Program

Title
Key Technologies of Dynamic Reconfigurable Chip

Principal Investigator
Self (Leibo Liu)

Co-Investigators
Prof. Jun Yang(Southeast University)
Prof. Yici Cai(Tsinghua University)

Period Held
2019-2023

Level of Support
Total cash

Total Cash
US$493,000 (i.e. 3396,000RMB)

Note: NSFC is similar to NSF in the US or EPSRC in the UK


3
Funding Organization
National Science and Technology Major Project (NSTMP)

Program
Kernal Electronic Devices, High-end General Application Chips, Fundamental Software Products

Title
System Solutions for Server CPUs Against Hardware Security Threats including Meltdown and Spectre Vulnerabilities

Principal Investigator
Self (Leibo Liu)

Co-Investigators
Dr. Jianfeng Pan (Qihu Company)
Prof. Ziyuan Zhu (Institute of Information Engineering, Chinese Academy of Sciences)
Prof. Hang Yuan (Beijing Institute of Information Science and Technology)

Period Held
2018-2019

Level of Support
Total cash

Total Cash
US$ 6,489,000 (i.e. 44,672,400 RMB)

Note: NSTMP is to achieve national goals, through the core technology, completed the major strategic product, the key technology and the major projects in a specified time.


4
Funding Organization
National Natural Science Foundation of China (NSFC)

Program
General program

Title
Physical Attack Countermeasures for Dynamic and Partial Reconfigurable Crypto Chip

Principal Investigator
Self (Leibo Liu)

Co-Investigators
None

Period Held
2017-2020

Level of Support
Total cash

Total Cash
US$116,900 (i.e. 760,000RMB)


5
Funding Organization
National Science and Technology Major Project (NSTMP)

Program
Kernal Electronic Devices, High-end General Application Chips, Fundamental Software Products

Title
IP Core of the Coarse-grained Reconfigurable Cryptographic Array

Principal Investigator
Self (Leibo Liu)

Co-Investigators
None

Period Held
2018-2020

Level of Support
Total cash

Total Cash
US$ 864,740 (i.e. 6,000,000 RMB)


6
Funding Organization
Intel Corporation

Program
Key Program for International Science and Technology Cooperation

Title
High Performance Computing Processor: Intel Xeon + Reconfigurable Computing Processor

Principal Investigator
Self (Leibo Liu)

Co-Investigators
None

Period Held
2016-2018

Level of Support
Total cash

Total Cash
US$80,000,000 (i.e. 549,000,000RMB)


7
Funding Organization
Ministry of Science and Technology (MOST)

Program
National High-tech Research and Development Program (the “863 Program”)

Title
General-purpose Reconfigurable Computing Processor： Architecture and Chip Design

Principal Investigator
Self (Leibo Liu)

Co-Investigators
None

Period Held
2012-2017

Level of Support
Total cash

Total Cash
US$1,744,615 (11,340,000RMB)

Note: As one of the most prestigious and important R&D programs in China, the “863 Program” is funded and administered by MOST, intended to stimulate the development of advanced science and technologies in a wide range of fields. The amount of funding is normally much higher than that from NSFC.


8
Funding Organization
Ministry of Science and Technology (MOST)

Program
National High-tech Research and Development Program (“863 Program”)

Title
Processing Element Array of Reconfigurable Multimedia Processor

Principal Investigator
Self (Leibo Liu)

Co-Investigators
None

Period Held
2009-2012

Level of Support
Total Cash

Total Cash
US$1,407,692 (9,150,000RMB)

[TEACHING]
1. Foundation Of Integrated Circuits I, course number: **, Mandatory Course for Undergraduates, Every Fall Semester since 2018.
2. Digital Integrated Circuit: Analysis & Design, course number: **, Mandatory Course for Undergraduates, Every Fall Semester since 2005.
3. VLSI Digital Signal Processing: course number **, Elective Course for Graduate Students, Every Spring Semester during 2006-2012, and 2017.
4. Digital Integrated Circuit: Analysis & Design, Massive Open Online Course (MOOC), Every Semester since 2015, Link: http://www.xuetangx.com/courses/course-v1:TsinghuaX+**_X+sp/about
[AWARDS AND HONORS]
RESEARCH
1. National Award for Technological Invention; The Second Prize; Winners: Shaojun Wei, Leibo Liu, Zhigang Mao, Longxing Shi, Shouyi Yin and Yuliang Deng; 2015 (Note: this is one of the three most prestigious national-level awards in science and technology awarded by the government of P. R. China).
2. Chinese Patent Golden Award, by the World Intellectual Property Organization (WIPO) and the State Intellectual Property Office of China (SIPO); Winners: Leibo Liu, Min Zhu, Yansheng Wang, Jianfeng Zhu, Jun Yang, Peng Cao, Longxing Shi, Shouyi Yin and Shaojun Wei; 2015 (Note: this is the highest government award for Intellectual Property in P. R. China).
3. Technological Invention Award by the Ministry of Education; The First Prize; Winners: Shaojun Wei, Longxing Shi, Leibo Liu, Shouyi Yin, Jun Yang and Weifeng He; 2014.
4. World Leading Internet Scientific and Technological Achievement: the 5^th World Internet Conference(WIC 2018)
5. Best Paper Nomination: Design Automation Conference 2017 (DAC’ 2017)
6. Design Contest Award: the 23^rd International Symposium on Low Power Electronics and Design 2017 (ISLPED 2017).
7. Science and Technology Progress Award by Jiangxi Province; The Second Prize; Winners: Shouyi Yin, Li Lin, Renjun Cheng, Leibo Liu, Bo Lan, Zhiming Zhang, Huiqin Wan and Yan Xu; 2014.
TEACHING
1. A First Prize Winner in the Teaching Competition for Young Faculties in Universities in Beijing, by the Government of Beijing, 2011 (Note: One of the 18 winners among 400 candidates from more than 50 Universities in Beijing).
2. Outstanding Teaching Award for Young Faculties in Tsinghua University, 2011 (Less than 10 young faculties are awarded each year in Tsinghua University).
3. Outstanding Undergraduate Course Award in Tsinghua University, 2010 (Less than 10 out of 100 undergraduate courses in Tsinghua University are identified as “top-quality undergraduate courses”).
4. A First Prize Winner in the Teaching Competition for Young Faculties in Tsinghua University, 2010.
5. Teaching Achievements Award in Tsinghua University, The Second Prize, Winners: Leibo Liu, Dong Wu, Xingjun Wu and Runde Zhou, 2012.
6. LIAO KAIYUAN Teaching Awards, Awarded by Tsinghua University Education Foundation, 2012.
[PUBLIC SERVICES]
ACADEMIA
Technical Program Committee (TPC) Vice Chair
l IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC) 2013
Deputy Editor-in-Chief
l 《IEEE Circuits and Systems Magazine》(IF=4.481)
Organizing Committee (OC) Chairs
l IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC) 2015, OC Chair
l IEEE International System-on Chip Conference (SOCC) 2015, Local OC Chair
l IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC) 2010, OC Vice Chair
Student Travel Grant Award Committee (STGA) Chair
l IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC) 2016
Workshop co-Chair
l Asian Non-Volatile Memory Workshop 2012
Deputy Director
l Cryptographic IC Technical Committee, Chinese Association for Cryptologic Research, 2018 - Present
Technical Program Committee (TPC) Member
l IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC), 2008 - Present
l Design Automation Conference, 2016-Present
l IEEE CAS Visual Signal Processing and Communication (VSPC), 2016-Present
l IEEE/ACM International Symposium on Microarchitecture (MICRO) 2017, External Review Committee Member
l Cryptographic Integrated Circuits conference 2016 (Crypto IC 2016) (The top-quality conference supported by Chinese Association for Cryptologic Research).
Executive Associate Editor-in-Chief
l “Frontiers of Information Technology & Electronic Engineering” (one of Transactions of CAE), Launched by Chinese Academy of Engineering, Science Citation Index (SCI).
UNIVERSITY & DEPARTMENT
Assistant Director
l Institute of Microelectronics, Tsinghua University, Beijing, China, 2009 – Present
Deputy Director
l Tsinghua Mobile-Computing Research Center (University-Level Research Center), Tsinghua University, Beijing, China, 2009 – Present
l IC Design Division, Institute of Microelectronics, Tsinghua University, Beijing, China
Expert Advisor
l Teaching Advisory Committee, Tsinghua University, Beijing, China, 2012-2014
l Students Science & Technology Innovation Contest, Tsinghua University, Beijing, China, 2012-2014
Student Advisor
l In charge of undergraduate affairs, Department of Microelectronics and Nanoelectronics, Tsinghua University, Beijing, China.
GOVERNMENT
Technical Assistant
l Information Science and Technology Expert Committee, National High-tech R&D Program (i.e. the “863 Program”), Ministry of Science and Technology, P. R. China, 2008-2015 (As one of the most prestigious and important R&D programs in China, the “863 Program” is funded and administered by the Ministry of Science and Technology (MOST), intended to stimulate the development of advanced science and technologies in a wide range of fields).
l Expert Committee, Major Research Plan for System-on-Chip, National Natural Science Foundation of China (NSFC), 2007-2010 (NNSFC is similar to NSF in the US or EPSRC in the UK).
[SELECTED INVITED TALKS]
l Reconfigurable Computing and Its Applications in Cryptographic Chips, a keynote talk in the Cryptographic Integrated Circuits Conference 2015 (Crypto IC 2015), Shanghai, China, September 2015, Invited by Technical Program Committee Chair, Prof. Xiaoyang Zeng (A top-quality conference in the fields of Crypto IC analysis and design supported by the Chinese Association for Cryptologic Research).
l System Platform Challenges for the Next Generation Mobile Computing, an invited talk at the Intel Development Forum 2010 (IDF 2010), Beijing, China, April 2010, Invited by Intel Corp.
l System Solutions for Server CPUs Against Hardware Security Threats including Meltdown and Spectre Vulnerabilities, a keynote talk in the Cryptographic Integrated Circuits Conference 2018(Crypto IC 2018), Beijing, China, August 2018, Invited by Conference Chair Prof. Zhihua Wang.
[PUBLICATIONS]
BOOKS
Leibo Liu, Guiqiang Peng, Shaojun Wei, “Massive MIMO Detection Algorithm and VLSI Architecture”, Springer Singapore, 2019. eBook ISBN：10. (In English, 450,000Words, 7 Chapters, 370 Pages).
Leibo Liu, Guiqiang Peng, Shaojun Wei, “Massive MIMO Detection Algorithm and VLSI Architecture--the application specific integrated circuit and dynamic reconfigurable chip design”, Springer Singapore, 2018. ISBN：978-7-03-060210-7. (In Chinese, 350,000Words, 7 Chapters, 312Pages).
Leibo Liu, Bo Wang, Shaojun Wei, “Reconfigurable Cryptographic Processor”, Springer Singapore, 2018. Hardcover ISBN：978-981-10-8898-8, eBook ISBN：978-981-10-8899-5. (In English, 500,000Words, 7 Chapters, 386 Pages).
Leibo Liu, Bo Wang, Shaojun Wei, “Reconfigurable Computing Processor for Cryptographic Algorithms”, China Science Press, September 2017. ISBN: 41 (In Chinese, 434,000Words, 7 Chapters, 337 Pages).
Shaojun Wei, Leibo Liu, Shouyi Yin, “Reconfigurable Computing”, China Science Press, July 2014, ISBN: 46 (In Chinese, 680,000Words, 14 Chapters, 550 Pages).
Leibo Liu, et al. “Approximate Arithmetic Circuits: Design and Evaluation” (Participated in writing the first chapter), Springer, 2018. ISBN-13: 18, ISBN-10: . (In English,).
Leibo Liu, et al. “The Book of Integrated Circuit Industry” (Participated in writing the tenth chapter), Publishing House of Electronics Industry, 2018. ISBN: 28
TEN SELECTED PUBLICATIONS IN RECENT THREE YEARS
Note: Supervised students are indicated with an underline “_”.
Corresponding authors are indicated with an asterisk “*”.
[1] L. Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei. “Jintide^？: A Hardware Security Enhanced Server CPU with Xeon^？ Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”. 31st Hot Chips: A Symposium on High Performance Chips( Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019
[2] L. Liu, J. Zhu, Z. Li, Y. Lu, Y. Deng, J. Han, S. Yin, S. Wei, “A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges and Applications”, ACM Computing Survey, 2019
[3] Z. Li, *L. Liu, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware,” in the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June, 2017, pp. 575-586. DOI: 10.1145/**.**
[4] G. Peng, L. Liu*, S. Zhou, S. Yin, S. Wei. "A 2.92 Gbps/W and 0.43 Gbps/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection." IEEEJournal of Solid State Circuits, 2019. DOI：10.1109/JSSC. 2019.** [In Press]
[5] Z. Li, *L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei. "FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory". In The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), October 12-16, 2019, Columbus, OH, USA.
[6] Q. Wang, *L. Liu, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment,” in the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June 2017, pp.57-57.DOI: 10.1145/**.** [Best Paper Nomination].
[7] B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, Z. Zhou, S. Wei, “Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 12, no. 2, pp. 309-322, Feb. 2017. DOI: 10.1109/TIFS.2016.**.
[8] L. Liu, J. Wang, J. Zhu, C. Deng, S. Yin, S. Wei, “TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 7, pp. 2143-2154, 2016. DOI: 10.1109/TPDS.2015.**.
[9] H. Mo, *L. Liu, W. Zhu, Q. Li, H. Liu, W. Hu, Y. Wang, S. Wei. “A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6, [Best Paper Nomination]
[10] N. Zhang, B. Yang, C. Chen, S. Yin, S. Wei, L. Liu*, "Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT", Conference on Cryptographic Hardware and Embedded Systems, (CHES 2020), Beijing, China, 14-17, September, 2020.(Accepted)
PUBLICATIONS IN RECENT YEARS
Note: Supervised students are indicated with an underline “_”.
Corresponding authors are indicated with an asterisk “*”.
Year 2020
---- Journal Papers (1 in total)
[1] N. Zhang, Q. Qin, H. Yuan, C. Zhou, S. Yin, S. Wei, L. Liu*, "NTTU: an Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication, " IEEE Transactions on Computers. DOI: 10.1109/TC.2019.**[In Press]
---- Conference Papers (1 in total)
[1] N. Zhang, B. Yang, C. Chen, S. Yin, S. Wei, L. Liu*, "Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT", Conference on Cryptographic Hardware and Embedded Systems, (CHES 2020), Beijing, China, 14-17, September, 2020.(Accepted)
Year 2019
---- Journal Papers (9 in total)
[1] L. Liu, J. Zhu, Z. Li, Y. Lu, Y. Deng, J. Han, S. Yin, S. Wei, “A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges and Applications”, ACM Computing Survey, 2019. DOI:10.1145/** [In Press]
[2] G. Peng, L. Liu*, S. Zhou, S. Yin, S. Wei. "A 2.92 Gbps/W and 0.43 Gbps/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection." IEEEJournal of Solid State Circuits, 2019. DOI：10.1109/JSSC. 2019.** [In Press]
[3] P. Wang, L. Liu*, S. Zhou, G. Peng, S. Yin, S. Wei. "Near-Optimal MIMO-SCMA Uplink Detection with Low-Complexity Expectation Propagation." IEEETransactions on Wireless Communications, 2019. DOI:10.1109/TWC. 2019.** [In Press]
[4] L. Wang, *L. Liu, J. Han, X. Wang, S. Yin, S. Wei. “Achieving Flexible Global Reconfiguration in NoCs using Reconfigurable Rings”. IEEE Transactions on Parallel and Distributed Systems (TPDS), 2019. DOI:10.1109/TPDS.2019. ** [In Press]
[5] H. Mo, *L. Liu, W. Zhu, Q. Li, H. Liu, S. Yin, S. Wei, “A Multi-task Hardwired Accelerator for Face Detection and Alignment”, IEEE Transactions on Circuits and Systems for Video Technology(TCSVT) [In Press]
[6] C. Deng, B. Wang, *L. Liu, M. Zhu, Y. Wu, H. Li, S. Yin, S. Wei. "A 60 Gbps-Level Coarse-Grained Reconfigurable Cryptographic Processor with Less than 1 W Power."IEEE Transactions on Circuits and Systems II: Express Briefs(TCAS-II), 2019. DOI:10.1109/TCSII.2019.** [In Press]
[7] M. Shi, P. Ouyang, S. Yin, L. Liu, S. Wei. "A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression."IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2019, 66(11): 1870-1874. DOI:10.1109/TCSII.2019.**
[8] Y. Liu, L. Liu, F. Lombardi, J. Han. "An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing."IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,27(9): 2213-2221. DOI:10.1109/TVLSI.2019.**
[9] S. Zheng, P. Ouyang, D. Song, X. Li, L. Liu, S. Wei, S. Yin. "An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning." IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2019. DOI:10.1109/TCSI.2019.** [In Press]
---- Conference Papers (9 in total)
[1] L. Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei. “Jintide^？: A Hardware Security Enhanced Server CPU with Xeon^？ Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”. 31st Hot Chips: A Symposium on High Performance Chips( Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019
[2] Z. Li, *L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei. "FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory". In The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), October 12-16, 2019, Columbus, OH, USA.
[3] H. Mo, *L. Liu, W. Zhu, Q. Li, H. Liu, W. Hu, Y. Wang, S. Wei. “A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6, [Best Paper Nomination]
[4] X. Man, *L. Liu, J. Zhu, S. Wei. “A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6
[5] H. Liu, *L. Liu, W. Zhu, Q. Li, H. Mo, S. Wei. “L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1-6
[6] H. Yan, Z. Li, *L. Liu, S. Yin, S. Wei. "Constructing Concurrent Data Structures on FPGA with Channels." InProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 172-177. ACM, 2019
[7] H. Yuan, W. Guo, Y. Cao, C. Deng, L. Liu, C. Chang, W. Ge, and F. Zhang. "A Reliable Physical Unclonable Function Based On Differential Charging Capacitors”, IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
[8] R. Guo, Y. Liu, S. Zheng, SY Wu, P. Ouyang, WS Khwa, X. Chen, JJ Chen, X. Li, L. Liu, M. Chang, S. Wei, S. Yin. "A 5.1 pJ/Neuron 127.3 us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS." In2019 Symposium on VLSI Circuits, pp. C120-C121. IEEE, 2019.
[9] H. Jiang, FJH Santiago, MS Ansari, L. Liu, BF Cockburn, F. Lombardi, J. Han. "Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints." InProceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 393-398. ACM, 2019.
Year 2018
---- Journal Papers (26 in total)
[1] L. Liu, B. Wang, C. Deng, M. Zhu, S. Yin, S. Wei. “Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), v 37, n 12, p 3081-3094, DOI: 10.1109/TCAD.2018.**.
[2] L. Liu, Q. Wang, W. Zhu, H. Mo, T. Wang, S. Yin, Y. Shi, S. Wei, “A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching,” IEEE Transactions on Circuits and Systems for Video Technology(TCSVT), DOI: 10.1109/TCSVT.2018.**. [In Press]
[3] L. Liu, W. Zhu, S. Yin, et al. “A Binary-Feature-Based Object Recognition Accelerator with 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), v 38, n 7, p 1265-1277, DOI:10.1109/TCAD. 2018.**.
[4] G. Peng, *L. Liu, S. Zhou, Y. Xue, S. Yin, S. Wei, “Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K-Best Detector for Large-Scale MIMO Systems,” IEEE Transactions on Signal Processing (TSP), v 66, n 7, p 1860-1875, DOI:10.1109/TSP.2018.**.
[5] H. Huang, *L. Liu, Q. Huang, Y. Chen, S. Yin, S. Wei. " Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), v 38, n 2, p 208-219, 2019. DOI: 10.1109/TCAD.2018.**.
[6] Z. Li, *L. Liu, Y. Deng, S. Yin, S. Wei. “Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution,” IEEE Computer Architecture Letters, v 17, n 2, p 147-150, DOI: 10.1109/LCA.2018.**.
[7] Y. Lu, *L. Liu, Y. Deng, J. Weng, S. Yin, Y. Shi and S. Wei. “Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays,” IEEE Transactions on Parallel and Distributed Systems(TPDS), v 29, n 10, p 2360-2372, DOI: 10.1109/TPDS.2018.**.
[8] H. Mo, *L. Liu, W. Zhu, S. Yin, S. Wei, “ Face Alignment with Expression- and Pose-Based Adaptive Initialization,” IEEE Transactions on Multimedia, v 21, n 4, p 943-956, 2019, DOI: 10.1109/TMM.2018.**.
[9] L. Wang, P. Lv, *L. Liu, et al. "A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD),v38, n9, p1771-1784, 2019, DOI: 10.1109/TCAD.2018.**.
[10] H. Jiang, L. Liu, Jonker P. P., et al. "A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers(TCAS-I), v 66, n 1, p 313-326, 2019, DOI: 10.1109/TCSI.2018. **
[11] S. Liang, S. Yin, L. Liu, W. Luk, S. Wei. “FP-BNN: Binarized neural network on FPGA,” Neurocomputing, vol. 275, pp. 1072-1086, March 2018. DOI: 10.1016/ j.neucom.2017.09.046.
[12] F. Tu, S. Yin, P. Ouyang, L. Liu, S. Wei. “Reconfigurable Architecture for Neural Approximation in Multimedia Computing,” IEEE Transactions on Circuits and Systems for Video Technology(TCSVT), v29, n3, p892-906, 2019, DOI:10.1109/TCSVT.2018.**.
[13] S. Yin, S. Tang, X. Li, P. Ouyang, F. Tu, L. Liu, S. Wei. “A high throughput acceleration for hybrid neural networks with efficient resource management on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), v38, n4, p678-691, 2019, DOI: 10.1109/TCAD.2018. **
[14] S. Yin, T. Lu, X. Yao, Z. Xie, L. Liu, S. Wei. “ Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis,” IEEE Access, v 6, p 7526-7540, 2018, DOI: 10.1109/ ACCESS.2018.**
[15] J. Gu, S. Yin, L. Liu, S. Wei. “ Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration,” IEEE Transactions on Parallel and Distributed Systems(TPDS), v29, n9, p2105-2120,2018, DOI: 10.1109/TPDS. 2018.**
[16] P. Ouyang, S. Yin, L. Liu, Y. Zhang, W. Zhao, S. Wei. “ A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT,” IEEE Transactions on Circuits and Systems I: Regular Papers(TCAS-I), v 65, n 10, p 3362-3375, 2018, DOI: 10.1109/TCSI.2018.**
[17] S. Yin, Z. Xie, C. Meng, P. Ouyang, L. Liu; S. Wei “Memory partitioning for parallel multipattern data access in multiple data arrays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), 2018, 37(2): 431-444. DOI: 10.1109/TCAD.2017.**
[18] J. Yan, S. Yin, F. Tu, L. Liu, S. Wei. “GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol. 37, no. 11, pp. 2519 - 2529, 2018. DOI: 10.1109/TCAD.2018.**
[19] S. Yin, T. Lu, Z. Xie, L. Liu, S. Wei. “Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(11):2345- 2357. DOI: 10.1109/TVLSI.2018.**
[20] S. Yin, S. Tang, X. Lin, P. Ouyang, F. Tu, L. Liu, J. Zhao, C. Xu, S. Li, Y. Xie, S. Wei. “Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory,” IEEE Transactions on Parallel and Distributed Systems (TPDS), 2019, 30(1): 146- 160. DOI: 10.1109/TPDS.2018. **
[21] P. Zhu, X. Song, L. Liu, Z. Wang, J. Han. "Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation," IEEE Access, v 6, pp:35292-35304, May 2018.DOI: 10.1109/ACCESS.2018.**.
[22] S. Yin, P. Ouyang, J. Yang, T. Lu, X. Li, L. Liu, S. Wei. "An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks with Flexible Data Bit Width." IEEE Journal of Solid-State Circuits(JSSC), 2019, 54(4): 1120- 1136. DOI: 10.1109/JSSC.2018.**.
[23] D. Liu, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng, S. Zhou. "Data-Flow Graph Mapping Optimization for CGRA with Deep Reinforcement Learning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), DOI: 10.1109/TCAD.2018.**. [In Press]
[24] S. Liu, H. Jiang, L. Liu, J. Han. "Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 11 (2018): 2530-2541.DOI: 10.1109/TCAD.2018.**.
[25] S. Yin, P. Ouyang, S. Tang, F. Tu, X. Li, S. Zheng, T. Lu, J. Gu, L. Liu, S. Wei. "A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications." IEEE Journal of Solid-State Circuits (JSSC), 2018, 53(4):968-982. DOI:10.1109/JSSC.2017.**
[26] UR Tida, C. Zhuo, L. Liu, Y. Shi. Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), 2018.

---- Conference Papers (13 in total)
[1] G. Peng, *L. Liu, Q. Wei, Y. Wang, S. Yin, S. Wei. “A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128*8 Massive MIMO Systems”, IEEE Asian Solid-State Circuits Conference (A-SSCC 2018), Tainan, Taiwan, 5-7 November.
[2] H. Jiang, L. Liu, L. Fabrizio, J. Han. “Adaptive approximation in arithmetic circuits: A low-power unsigned divider design” , 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 19-23 March 2018, 1411-1416. DOI: 10.23919/DATE.2018.**.
[3] F. Tu, W. Wu, S. Yin, L. Liu, S. Wei, "RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM", ACM/IEEE, International Symposium on Computer Architecture (ISCA 2018), Los Angeles, CA, USA, pp: 340-352. DOI: 10.1109/ISCA.2018.00037.
[4] S. Zheng, Y. Liu, S. Yin, L. Liu, S. Wei, " An Efficient Kernel Transformation Architecture for Binary- and Ternary-Weight Neural Network Inference," 55th Automation Conference (DAC), San Francisco, CA, USA, 24-28 June 2018, 1-6.
[5] X. Lin, S. Yin, F. Tu, L. Liu, X. Li, S. Wei, " LCP: a Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA", 55th Design Automation Conference (DAC), San Francisco, CA, USA, 24-28 June 2018, 1-6.
[6] S. Yin, P. Ouyang, J. Yang, T. Lu, X. Li, L. Liu, S. Wei. “An Ultra-high Energy-efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28nm CMOS”, 2018 Symposia on VLSI Technology and Circuits (VLSI), Honolulu, HI, June 18-22, 2018.
[7] S. Yin, P. Ouyang, S. Zheng, D. Song, X. Li, L. Liu, S. Wei. “A 141uW, 2.46 pJ/Neuron Binarized Convolutional Neural Network based Self-learning Speech Recognition Processor in 28nm CMOS”, 2018 Symposia on VLSI Technology and Circuits (VLSI), Honolulu, HI, June 18-22, 2018.
Year 2017
---- Journal Papers (17 in total)
[1] L. Liu, C. Yang, S. Yin, S. Wei, “CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 6, pp. 1171-1184, June 2018. DOI: 10.1109/TCAD.2017.**.
[2] L. Liu, Z. Zhou, S. Wei, M. Zhu, S. Yin, S. Mao, “DRMaSV: Enhanced Capability against Hardware Trojans in Coarse Grained Reconfigurable Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018, 37(4): 782-795. DOI: 10.1109/TCAD.2017.**.
[3] L. Liu, Z. Li, C. Yang, C. Deng, S. Yin, S. Wei, “HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing,” IEEE Transactions on Circuits and Systems II: Express Briefs(TCAS-II), 2018, 65(3): 381-385. DOI: 10.1109/TCSII.2017.**.
[4] L. Liu, C. Deng, Z. Li, S. Yin and S. Wei. “Reconfigurable Computing System: A Project-Based Course for Graduate Students,” The International Journal of Engineering Education(IJEE), vol. 33, no. 2(A), pp.622-628,2017.
[5] L. Liu, Y. Chen, C. Deng, S. Yin, S. Wei. “Implementation of In-Loop Filter for HEVC Decoder on Reconfigurable Processor,” Institution of Engineering and Technology(IET) Image Processing, vol.11, no.9, pp.685-692, September, 2017. DOI: 10.1049/iet-ipr.2016.0143
[6] G. Peng, *L. Liu, S. Zhou, S. Yin, S. Wei, “A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for 128*8 64-QAM Massive MIMO in 65 nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS- I), 2018, 65(5): 1717-1730. DOI: 10.1109/TCSI.2017.**.
[7] G. Peng, *L. Liu, P. Zhang, S. Yin, S. Wei, “Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture,” IEEE Transactions on Signal Processing (TSP), vol.65, no.14, pp.3775-3788, April 2017. DOI: 10.1109/TSP.2017.**.
[8] C. Wu, C. Deng, *L. Liu, J. Han, J. Chen, S. Yin, S. Wei, “A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 3, pp. 662-676, March 2017. DOI: 10.1109/TPDS.2016.**.
[9] B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, Z. Zhou, S. Wei, “Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 12, no. 2, pp. 309-322, Feb. 2017. DOI: 10.1109/TIFS.2016.**.
[10] C. Yang, *L. Liu, K. Luo, S. Yin, S. Wei, “CIACP: A Correlation- and Iteration-Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 1, pp. 29-43, January 2017. DOI: 10.1109/TPDS.2016.**.
[11] C. Deng, *L. Liu, Y. Liu, S. Yin, S. Wei, “PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC,” IEEE Transactions on Circuits and Systems II: Express Briefs(TCAS-II), vol. 64, no. 5, pp. 540-544, May 2017, DOI: 10.1109/TCSII.2016.**.
[12] S. Yin, P. Ouyang, X. Dai, L. Liu, S. Wei, “An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation,” IEEE Systems Journal, vol. 11, no. 1, pp. 260-271, May 2017. DOI: 10.1109/JSYST.2015.**.
[13] S. Yin, Z. Xie, C. Meng, P. Ouyang, L. Liu, S. Wei. “Memory Partitioning for Parallel Multi-pattern Data Access in Multiple Data Arrays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. DOI: 10.1109/TCAD.2017.**.
[14] F. Tu, S. Yin, P. Ouyang, S. Tang, L. Liu, S. Wei. “Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol.25, no.8, pp.2220-2223, August, 2017. DOI: 10.1109/JSYST.2015.**.
[15] S. Yin, X. Yao, T. Lu, D. Liu, J. Gu, L. Liu, S. Wei. “Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.28, no.9, pp.2471-2485, September, 2017, DOI: 10.1109/TPDS.2017.**.
[16] H. Jiang, C. Liu, L. Liu, et al. “A review, classification, and comparative evaluation of approximate arithmetic circuits.” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol.13, no.4 pp.60, August, 2017. DOI: 10.1145/**
[17] Xu W, Yin S, Zhang Z, L. Liu, et al. Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion[J]. IEEE Access, 2017, 5: 26604-26613. DOI: 10.1109/ACCESS.2017.**
---- Conference Papers (21 in total)
[1] Z. Li, *L. Liu, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware,” in the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June, 2017, pp. 575-586.DOI: 10.1145/**.**
[2] Y. Lu, *L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng and S. Wei, “Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution,” in the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June, 2017, pp.71-71. DOI: 10.1145/**.**.
[3] Q. Wang, *L. Liu, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment,” in the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June 2017, pp.57-57.DOI: 10.1145/**.** [Best Paper Nomination].
[4] S. Yin, P. Ouyang, S. Tang, F. Tu, X. Li, L. Liu, S. Wei. “A 1.06-to-5.09 TOPS/W Reconfigurable Hybrid-Neural-Network Processor for Deep Learning Applications,” in the 2017 Symposia on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 5-8, 2017.
[5] S. Yin, P. Ouyang, S. Tang, F. Tu, X. Li, L. Liu, S. Wei. “High Energy-Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications,” in the 23^rd International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July, 2017[Design Contest Award].
[6] S. Yin, D. Liu, L. Sun, X. Lin, L. Liu, S. Wei, “Learning convolutional neural networks for data-Flow graph mapping on spatial programmable architectures,” in the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California, USA, Feb. 2017, pp.295-295.DOI: 10.1145/**.**.
[7] T. Lu, S. Yin, X. Yao, Z. Xie, L. Liu, S. Wei, “Joint modulo scheduling and memory partitioning with multi-bank memory for high-level synthesis,” in the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California, USA, Feb. 2017,pp 290-290. DOI: 10.1145/**.**.
[8] J. Guo, S. Yin, P. Ouyang, L. Liu, S. Wei. “Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA,” in the 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), California, USA, April 2017, pp. 31-31. DOI: 10.1109/FCCM.2017.13.
[9] J. Gu, S. Yin, L. Liu, S. Wei. “Energy-aware loops mapping on multi-vdd CGRAs without performance degradation,” in the 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, pp.312-317. DOI: 10.1109/ASPDAC.2017.**.
[10] P. Ouyang, S. Yin, C. Xing, L. Liu, S. Wei. “A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation,” in the 2017 ACM Great Lakes Symposium on VLSI, pp. 287-292.
[11] T. Lu, S. Yin, X. Yao, Z. Xie, L. Liu, S. Wei. “Memory fartitioning-based modulo scheduling for high-level synthesis,” in the2017 IEEE International Symposium on Circuits and Systems (ISCAS),pp. 1-4.
[12] S. Yin, D. Liu, L. Sun, L. Liu, S. Wei. “DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach,” in the2017 IEEE International Symposium on Circuits and Systems (ISCAS),pp. 1-4.
[13] S. Yin, J. Duan, P. Ouyang, L. Liu, S. Wei. "Multi-CNN and decision tree based driving behavior evaluation", The 32nd ACM SIGAPP Symposium On Applied Computing(SAC)2017, Marrakech, Morocco, 2017.04.04-2017.04.06. DOI: 10.1145/**.**
[14] H. Jiang, L. Liu, J. Han. Special session paper: an efficient hardware design for cerebellar models using approximate circuits[C]//Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2017 International Conference on IEEE, 2017: 1-2. DOI: 10.1145/**.**
[15] S. Tang, S. Yin, S. Zheng, et al. AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs[C]//Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2017 IEEE 6th. IEEE, 2017: 1-6. DOI: 10.1109/NVMSA.2017.**

Year 2016
---- Journal Papers (16 in total)
[1] L. Liu, J. Wang, J. Zhu, C. Deng, S. Yin, S. Wei, “TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 7, pp. 2143-2154, 2016. DOI: 10.1109/TPDS.2015.**.
[2] B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, S. Wei, “Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 11, no. 6, pp. 1151-1164, 2016. DOI: 10.1109/TIFS.2016.**.
[3] W. Zhu, *L. Liu, G. Jiang, S. Yin, S. Wei, “A 135 fps 1080p 87.5 mW Binary Descriptor Based Image Feature Extraction Accelerator,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 26, no. 8, pp. 1532-1543, 2016. DOI: 10.1109/TCSVT.2015.**.
[4] P. Zhu, J. Han, L. Liu, F. Lombardi, “Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation,” IEEE Transactions on Reliability (TR), vol. 65, no. 3, pp. 1612-1623, 2016. DOI: 10.1109/TR.2016.**.
[5] S. Yin, X. Lin, L. Liu, S. Wei, “Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 11, pp. 3199-3213, 2016. DOI: 10.1109/TPDS.2016.**.
[6] S. Yin, J. Gu, D. Liu, L. Liu, S. Wei, “Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual-Vdd CGRAs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 9, pp. 1475-1488, 2016. DOI: 10.1109/TCAD.2015.**.
[7] S. Yin, D. Liu, Y. Peng, L. Liu, S. Wei, “Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 2, pp. 507-520, 2016. DOI: 10.1109/TVLSI.2015.**.
[8] S. Yin, P. Ouyang, T. Chen, L. Liu, S. Wei, “A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 4, pp. 1305-1318, 2016. DOI: 10.1109/TVLSI.2015.**.
[9] S. Yin, W. Xu, J. Li, L. Liu, S. Wei, “CWFP: novel Collective Writeback and Fill Policy for Last-Level DRAM Cache,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 7, pp. 2548-2561, 2016. DOI: 10.1109/TVLSI.2015.**.
[10] S. Yin, P. Ouyang, L. Liu, S. Wei, “A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation,” IEEE Transactions on Circuits and Systems II. Express Briefs (TCAS-II), vol. 63, no. 7, pp. 668-672, 2016. DOI: 10.1109/TCSII.2016.**.
[11] S. Yin, P. Zhou, L. Liu, S. Wei, “Trigger-Centric Loop Mapping on CGRAs,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 5, pp. 1998-2002, 2016. DOI: 10.1109/TVLSI.2015.**.
[12] S. Yin, X. Yao, D. Liu, L. Liu, S. Wei, “Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 5, pp. 1895-1908, 2016. DOI: 10.1109/TVLSI.2015.**.
[13] B. Wang, *L. Liu, “Dynamically reconfigurable architecture for symmetric ciphers,” Science China Information Sciences, vol. 59, no. 5, April 1, 2016. DOI: 10.1007/s11432-015-5381-z.
[14] L. Liu, D. Wang, Y. Chen, M. Zhu, S. Yin, S. Wei, “An implementation of multiple-standard video decoder on a mixed-grained reconfigurable computing platform,” IEICE Transactions on Information and Systems, v E99D, n 5, p 1285-1295, May 2016. DOI: 10.1587/transinf.2015EDP7369
[15] P. Ouyang, S. Yin, C. Deng, L. Liu, S. Wei, “A fast face detection architecture for auto-focus in smart-phones and digital cameras,” Science China Information Sciences, vol. 59, no. 12, pp. 1-13, Dec. 2016. DOI: 10.1007/s11432-015-5312-z.
[16] S. Liang, S. Yin, L. Liu, Y. Guo, S. Wei, “A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration,” IEEE Computer Architecture Letters, vol. 15, no. 2, pp. 69-72, JUL-DEC 2016. DOI: 10.1109/LCA.2015.**.
---- Conference Papers (4 in total)
[1] C. Yang, *L. Liu, S. Yin, and S. Wei, “Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays,” in the 53rd Annual Design Automation Conference (DAC 2016), Austin, TX, United States, June, 2016, pp. 1-6. DOI: 10.1145/**.**
[2] S. Yin, X. Yao, T. Lu, L. Liu, S. Wei, “Joint Loop Mapping and Data Placement for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory,” in the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, United states, Nov. 2016, pp. 1-8, DOI: 10.1145/**.**.
[3] S. Yin, Z. Xie, C. Meng, L. Liu, S. Wei, “Multi-bank Memory Optimization for Parallel Data Access in Multiple Data Arrays,” in the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, United states, Nov. 2016, pp. 1-8, DOI: 10.1145/**.**.
[4] X. Lin, S. Yin, L. Liu, S. Wei, “Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures,” in the 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, Macao, Jan. 2016, pp. 456-461. DOI: 10.1109/ASPDAC.2016.**.
Year 2015
---- Journal Papers (22 in total)
[1] L. Liu, D. Wang, M. Zhu, Y. Wang, S. Yin, P. Cao, J. Yang, S. Wei, “An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding,” IEEE Transactions on Multimedia (TMM), vol. 17, no. 10, pp. 1706-1720, 2015. DOI: 10.1109/TMM.2015.**.
[2] L. Liu, C. Wu, C. Deng, S. Yin, Q. Wu, J. Han, S. Wei, “A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 11, pp. 2566-2580, 2015. DOI: 10.1109/TVLSI.2014.**.
[3] C. Wu, C. Deng, *L. Liu, J. Han, J. Chen, S. Yin, S. Wei, “An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 8, pp. 1264-1277, 2015. DOI: 10.1109/TCAD.2015.**.
[4] J. Zhu, *L. Liu, S. Yin, X. Yang, S. Wei, “A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 9, pp. 1700-1709, 2015. DOI: 10.1109/TVLSI.2014.**.
[5] G. Jiang, *L. Liu, W. Zhu, S. Yin, S. Wei, “A 181 GOPS AKAZE accelerator employing discrete-time cellular neural networks for real-time feature extraction,” Sensors, vol. 15, no. 9, pp. 22509-22529, 2015. DOI: 10.3390/s.
[6] P. Zhu, J. Han, L. Liu, F. Lombardi, “A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures,” IEEE Transactions on Reliability (TR), vol. 64, no. 3, pp. 878-892, 2.15. DOI: 10.1109/TR.2015.**.
[7] J. Han, E. Leung, L. Liu, F. Lombardi, “A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 8, pp. 1562-1566, 2015. DOI: 10.1109/TVLSI.2014.**.
[8] D. Liu, S. Yin, Y. Peng, L. Liu, S. Wei, “Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 11, pp. 2581-2594, 2015. DOI: 10.1109/TVLSI.2014.**.
[9] P. Ouyang, S. Yin, Y. Zhang, L. Liu, S. Wei, “A Fast Integral Image Computing Hardware Architecture with High Power and Area Efficiency,” IEEE Transactions on Circuits and Systems II. Express Briefs (TCAS-II), vol. 62, no. 1, pp. 75-79, 2015. DOI: 10.1109/TCSII.2014.**.
[10] L. Liu, W. Zhang, C. Deng, S. Yin, S. Wei, “BriGuard: a lightweight indoor intrusion detection system based on infrared light spot displacement,” IET Science, Measurement & Technology, vol. 9, no. 3, pp. 306-314, 2015. DOI: 10.1049/iet-smt.2013.0171.
[11] C. Wu, C. Deng, *L. Liu, S. Yin, J. Han, S. Wei, “Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints,” Science China Information Sciences, vol. 58, no. 8, pp.1-14, 2015. DOI: 10.1007/s11432-014-5248-8.
[12] C. Yang, *L. Liu, Y. Wang, S. Yin, P. Cao, S. Wei, “Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array,” Journal of Circuits, Systems and Computers, vol. 24, no. 03, 2015. DOI: 10.1142/S02**437.
[13] Y. Ren, *L. Liu, S. Yin, J. Han, S. Wei, “Efficient fault-tolerant topology reconfiguration using a maximum flow algorithm,” ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 3, pp. 1-24, May 2015. DOI: 10.1145/**.
[14] P. Ouyang, S. Yin, L. Liu, S. Wei, “Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 23, no. 12, pp. 3085-3098, Dec. 2015. DOI:10.1109/TVLSI.2014.**.
[15] Z. Zhang, S. Yin, L. Liu, S. Wei, “A real-time time-consistent 2D-to-3D video conversion system using color histogram,” IEEE Transactions on Consumer Electronics, vol. 61, no. 4, pp. 524-530, Nov. 2015. DOI: 10.1109/TCE.2015.**.
[16] W. Xu, S. Yin, L. Liu, Z. Liu, S. Wei, “High-performance motion estimation for image sensors with video compression,” Sensors, vol. 15, no. 8, pp. 20752-20778, Aug. 2015. DOI: 10.3390/s.
[17] S. Yin, H. Dong, G. Jiang, L. Liu, S. Wei, “A Novel 2D-to-3D video conversion method using time-coherent depth maps,” Sensors, vol. 15, no. 7, pp. 15246-15264, June 2015. DOI: 10.3390/s.
[18] D. Liu, S. Yin, L. Liu, S. Wei, “Mapping multi-level loop nests onto CGRAs using polyhedral optimizations,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E98A, no. 7, pp. 1419-1430, July 2015. DOI: 10.1587/transfun.E98.A.1419.
[19] Y. Peng, S. Yin, L. Liu, S. Wei, “Battery-aware loop nests mapping for CGRAs,” IEICE Transactions on Information and Systems, vol. E98D, no. 2, pp. 230-242, Feb. 2015. DOI: 10.1587/transinf.2014RCP0003.
[20] B. Xu, S. Yin, L. Liu, S. Wei, “Low-power loop parallelization onto CGRA utilizing variable dual VDD,” IEICE Transactions on Information and Systems, vol. E98D, no. 2, pp. 243-251, Feb. 2015. DOI: 10.1587/transinf.2014RCP0004 .
[21] R. Shi, S. Yin, L. Liu, Q. Liu, S. Liang, S. Wei, “The implementation of texture-based video up-scaling on coarse-grained reconfigurable architecture,” IEICE Transactions on Information and Systems, vol. E98D, no. 2, pp. 276-287, Feb. 2015. DOI: 10.1587/transinf.2014RCP0010.
[22] S. Yin, P. Ouyang, L. Liu, Y. Guo, S. Wei, “Fast traffic sign recognition with a rotation invariant binary pattern based feature,” Sensors, vol. 15, no. 1, pp. 2161-2180, Jan. 2015. DOI: 10.3390/s.
---- Conference Papers (15 in total)
[1] J. Wang, *L. Liu, J. Zhu, S. Yin, S. Wei, “Acceleration of control flows on Reconfigurable Architecture with a composite method,” in the 52rd Annual Design Automation Conference(DAC 2015), San Francisco, CA, USA, Jun. 2015, pp. 1-6, DOI: 10.1145/**.**.
[2] G. Jiang, *L. Liu, W. Zhu, S. Yin, S. Wei, “A 127 fps in full HD accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction,” in the 52rd Annual Design Automation Conference(DAC 2015), San Francisco, CA, USA, Jun. 2015, pp. 1-6. DOI:10.1145/**.**
[3] C. Meng, S. Yin, P. Ouyang, L. Liu, S. Wei, “Efficient memory partitioning for parallel data access in multidimensional arrays,” in the 52rd Annual Design Automation Conference(DAC 2015), San Francisco, CA, USA, Jun. 2015, pp. 1-6. DOI: 10.1145/**.**
[4] S. Yin, P. Zhou, L. Liu, S. Wei, “Acceleration of nested conditionals on CGRAs via trigger scheme,” in the 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, Nov. 2015, pp. 597-604. DOI: 10.1109/ICCAD.2015.**.
[5] L. Liu, Y. Ren, C. Deng, S. Yin, S. Wei, J. Han, “A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures,” in the 2015 20st Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2015, pp. 48-53, DOI: 10.1109/ASPDAC.2015.**.
[6] F. Tu, S. Yin, P. Ouyang, L. Liu, S. Wei, “RNA. A reconfigurable architecture for hardware neural acceleration,” in the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp. 694-700.
[7] S. Yin, J. Li, L. Liu, S. Wei, Y. Guo, “Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache,” in the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 2015, pp. 187-192.
[8] Y. Peng, S. Yin, L. Liu, S. Wei, “Battery-aware mapping optimization of loop nests for CGRAs,” in the 2015 20st Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2015, pp. 767-772, DOI: 10.1109/ASPDAC.2015.**.
[9] S. Yin, P. Ouyang, L. Liu, S. Wei, “A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space,” in the 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sep. 2015, pp. 1-4. DOI: 10.1109/CICC.2015.**.
[10] S. Yin, D. Liu, L. Liu, S. Wei, Y. Guo, “Joint affine transformation and loop pipelining for mapping nested loop on CGRAs,” in the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 2015, pp. 115-120.
[11] L. Liu, Y. Chen, D. Wang, M. Zhu, S. Yin, S. Wei, “A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding,” in the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 2015, pp. 267-267. DOI: 10.1145/**.**.
[12] C. Yang, *L. Liu, S. Yin, S. Wei, “Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array,” in the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 2015, pp. 263-263. DOI: 10.1145/**.**.
[13] J. Wang, *L. Liu, J. Zhu, S. Yin, S. Wei, “A novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture,” in the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 2015, pp. 270-270. DOI: 10.1145/**.**.
[14] B. Wang, *L. Liu, “REPROC. A Dynamically Reconfigurable Architecture for Symmetric Cryptography,” in the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, Feb. 2015, pp. 269-269. DOI: 10.1145/**.**.
[15] B.Wang, *L. Liu, “A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing,” in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1182-1185, DOI: 10.1109/ISCAS.2015.**
Year 2014
---- Journal Papers (17 in total)
[1] L. Liu, D. Wang, S. Yin, Y. Chen, M. Zhu, S. Wei, “SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 12, pp. 2635-2648, 2014. DOI: 10.1109/TVLSI.2013.**.
[2] L. Liu, W. Zhu, S. Yin, E. Y. Tang, P. Peng, “An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices,” IEEE Transactions on Consumer Electronics (TCE), vol. 60, no. 1, pp. 137-145, 2014. DOI: 10.1109/TCE.2014.**.
[3] J. Zhu, *L. Liu, S. Yin, S. Wei, “Low-Power Reconfigurable Processor Utilizing Variable Dual V_DD,” IEEE Transactions on Circuits and Systems II. Express Briefs (TCAS-II), vol. 60, no. 4, pp. 217-221, 2013. DOI: 10.1109/TCSII.2013.**.
[4] Y. Wang, *L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, S. Wei, “On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 5, pp. 983-994, 2014. DOI: 10.1109/TVLSI.2013.**.
[5] P. Zhu, J. Han, L. Liu, J. Zuo, “A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates,” IEEE Transactions on Reliability (TR), vol. 63, no. 2, pp. 480-494, 2014. DOI: 10.1109/TR.2014.**.
[6] L. Liu, Y. Chen, S. Yin, L. Zhou, H. Yuan, S. Wei, “Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system,” Science China Information Sciences, vol. 57, no. 8, pp. 1-14, .2014. DOI: 10.1007/s11432-013-4979-2.
[7] L. Liu, Y. Wang, S. Yin, M. Zhu, X. Wang, S. Wei, “Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture,” Science China Information Sciences, vol. 57, no. 10, pp. 1-18, 2014. DOI: 10.1007/s11432-013-4973-8.
[8] L. Liu, Y. Chen, D. Wang, S. Yin, X. Wang, L. Wang, H. Lei, P. Cao, S. Wei, “Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor,” Science China Information Sciences, vol. 57, no. 8, pp. 1-14, 2014. DOI: 10.1007/s11432-013-4968-5.
[9] S. Cai, *L. Liu, S. Yin, R. Zhou, W. Zhang, S. Wei, “Optimization of speeded-up robust feature algorithm for hardware implementation,” Science China Information Sciences, vol. 57, no. 4, pp. 1-15, 2014. DOI: 10.1007/s11432-013-4946-y.
[10] C. Yang, *L. Liu, S. Yin, et al. “Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays,” Science China Physics, Mechanics & Astronomy, 2014, 57(12). 2214-2227. DOI: 10.1007/s11433-014-5610-2.
[11] L. Liu, Y. Chen, S. Yin, H. Lei, G. He, S. Wei, “An architecture of entropy decoder, inverse quantiser and predictor for multi-standard video decoding,” International Journal of Electronics, v 101, n 7, p 877-893, July 3, 2014. DOI: 10.1080/**.2013.794481.
[12] R. Zhou, *L. Liu, S. Yin, A. Luo, X. Chen, S. Wei, “A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator,” International Journal of Electronics, v 101, n 11, p 1580-1594, November 2, 2014. DOI: 10.1080/**.2014.888773.
[13] R. Zhou, *L. Liu, S. Wei, “A high performance parallel computing architecture for robust image features,” International Journal of Electronics, v 101, n 3, p 391-404, March 4, 2014. DOI: 10.1080/**.2013.780306.
[14] S. Y. Yin, S. J. Shao, L. Liu, S. J. Wei, “MapReduce inspired loop mapping for coarse-grained reconfigurable architecture,” Science China Information Sciences, vol. 57, no. 12, pp. 1-14, Dec. 2014. DOI: 10.1007/s11432-014-5198-1.
[15] S. Yin, X. Dai, P. Ouyang, L. Liu, S. Wei, “A multi-modal face recognition method using complete local derivative patterns and depth maps,” Sensors, vol. 14, no. 10, pp. 19561-19581, Oct. 2014. DOI: 10.3390/s.
[16] S. Yin, Z. Zhang, Y. Hu, L. Liu, S. Wei, “Mixed-level modeling methodology for Network-on-Chip architecture exploration,” Chinese Journal of Electronics, vol. 23, no. 3, pp. 468-473, July 2014.
[17] W. Zhu, *L. Liu, S. Yin, S. Hu, E. Y. Tang, S. Wei, “Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices,” International Journal of Electronics, vol. 101, no. 5, pp. 621-635, May 2014. DOI: 10.1080/**.2013.794482
---- Conference Papers (4 in total)
[1] S. Yin, P. Ouyang, L. Liu, S. Wei, “Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms,” in the 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, Mar. 2014. pp. 1-6. DOI: 10.7873/DATE.2014.350.
[2] C. Yang, *L. Liu, Y. Wang, S. Yin, P. Cao, S. Wei, “Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor,” in the 2014 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, Sep. 2014, pp. 1-4. DOI: 10.1109/FPL.2014.**.
[3] D. Liu, S. Yin, L. Liu, S. Wei, “Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures,” in the 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, USA, May 2014, pp. 32-32. DOI: 10.1109/FCCM.2014.19.
[4] W. Zhu, *L. Liu, S. Yin, Y. Dong, S. Wei, Eugene Y. Tang, Jiqiang Song, Jinzhan Peng, “A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing,” in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Victoria, Australia, Jun. 2014, pp. 2527-2530, DOI: 10.1109/ISCAS.2014.**.
Year 2013
---- Journal Papers (15 in total)
[1] L. Liu, W. Jia, S. Yin, D. Wang, G. Sun, E. Tang, S. Wei, “ReSSIM: A mixed-level simulator for dynamic coarse-grained reconfigurable processor,” Science China Information Sciences, vol. 56, no. 6, pp. 1-16, 2013. DOI: 10.1007/s11432-013-4812-y.
[2] Y. Wang, *L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, S. Wei, “Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture,” Science China Information Sciences, vol. 56, no. 11, pp. 1-20, 2013. DOI: 10.1007/s11432-013-4842-5.
[3] W. Zhang, *L. Liu, S. Yin, R. Zhou, S. Cai, S. Wei, “An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video,” Science China Information Sciences, vol. 56, no. 7, pp. 1-14, 2013. DOI: 10.1007/s11432-013-4786-9.
[4] Y. Ren, L. Liu, S. Yin, J. Han, Q, Wu, S. Wei, “A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration,” Journal of Systems Architecture(JSA), vol.59, no. 7, pp. 482-491, 2013. DOI: 10.1016/j.sysarc.2013.03.010.
[5] M. Zhu, *L. Liu, S. Yin, X. Wang, S. Wei, “Implementation of high throughput hardware efficient one-cycle cabac decoder,” International Journal of Electronics, v 100, n 11, p 1557-1568, November 1, 2013. DOI: 10.1080/**.2012.751323.
[6] Y. Wang, *L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, S. Wei, “The organization of on-chip data memory in one coarse-grained reconfigurable architecture,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v E96-A, n 11, p 2218-2229, November 2013. DOI: 10.1587/transfun.E96.A.2218.
[7] Z. Zhang, S. Yin, L. Liu, S. Wei, “An inductive-coupling interconnected application-specific 3D NoC design,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96A, no. 12, p 2633-2644, Dec. 2013. DOI: 10.1587/transfun.E96.A.2633
[8] S. Yin, R. Shi, L. Liu, S. Wei, “Battery-Aware task mapping for coarse-grained reconfigurable architecture,” IEICE Transactions on Information and Systems, vol. E96D, no. 12, pp. 2524-2535, Dec. 2013. DOI: 10.1587/transinf.E96.D.2524.
[9] S. Yin, D. Liu, L. Liu, S. Wei, “Affine transformations for communication and reconfiguration optimization of mapping loop nests on CGRAs,” IEICE Transactions on Information and Systems, vol. E96D, no. 8, pp. 1582-1591, Aug. 2013. DOI: 10.1587/transinf.E96.D.1582.
[10] J. Zhang, S. Yin, P. Ouyang, L. Liu, S. Wei, “Concurrent detection and recognition of individual object based on colour and p-SIFT features,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96A, no. 6, pp. 1357-1365, June 2013. DOI: 10.1587/transfun.E96.A.1357.
[11] H. Gao, L. Liu, S. Wei, “Parallelization of computing-intensive tasks of SIFT algorithm on a reconfigurable architecture system,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96A, no. 6, pp. 1393-1402, June 2013. DOI: 10.1587/transfun.E96.A.1393 .
[12] H. K. Nguyen, P. Cao, X. X. Wang, J. Yang, L. X. Shi, M. Zhu, L. Liu, S. J. Wei, “Hardware software co-design of H.264 baseline encoder on coarse-grained dynamically reconfigurable computing system-on-chip,” IEICE Transactions on Information and Systems, vol. E96D, no. 3, pp. 601-615, March 2013. DOI: 10.1587/transinf.E96.D.601.
[13] S. Y. Yin, L. Liu, R. Y. Zhou, Z. F. Sun, S. J. Wei, “Design of Wireless Multi-media Sensor Network for Precision Agriculture,” China Communications,vol.10,no.2,pp. 71-88,Feb. 2013.
[14] S. Y. Yin, J. W. Cui, L. Liu, S. J. Wei, “Calibration techniques for low-power wireless multiband transceiver,” International Journal of Distributed Sensor Networks, vol. 2013, Article ID 754206, pp. 1-8, 2013. DOI: 10.1155/2013/754206.
[15] D. Wang, P. Ren, *L. Liu, “A high-throughput fixed-point complex divider for FPGAs,” IEICE Electronics Express, vol. 10, no. 4, pp. 1-8, 2013. DOI: 10.1587/elex.10.**.
---- Conference Papers (5 in total)
[1] L. Liu, C. Deng, D. Wang, M. Zhu, S. Yin, P. Cao, S. Wei, “An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications,” in the IEEE 2013 Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sep. 2013, pp. 1-4. DOI: 10.1109/CICC.2013.**.
[2] L. Liu, W. Zhang, C. Deng, S. Yin, “SURFEX. A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process,” in the IEEE 2013 Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sep. 2013, pp. 1-4.DOI: 10.1109/CICC.2013.**.
[3] D. Liu, S. Yin, L. Liu, S. Wei, “Polyhedral model based mapping optimization of loop nests for CGRAs,” in the 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, USA, May 29 – Jun. 2013, pp. 1-8.
[4] L. Liu, Y. Chen, S. Yin, D. Wang, Xing Wang, S. Wei, L, Zhou, H. Lei, P. Cao, “Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor,” in the 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 2013, pp. 897-900, DOI: 10.1109/ISCAS.2013.**
[5] Y. Ren, *L. Liu, S. Yin, Q. Wu, S. Wei, J. Han, “A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration,” in the 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 2013, pp. 1793-1796, DOI: 10.1109/ISCAS.2013.**
Before 2013
[1] L. Liu, N. Chen, H. Meng, L. Zhang, Z. Wang, H. Chen, “A VLSI architecture of JPEG2000 encoder,” IEEE Journal of Solid-State Circuits(JSSC), vol. 39, no. 11, pp. 2032-2040, Nov. 2004. DOI: 10.1109/JSSC.2004.831492.
[2] L. Wang, L. Liu, H. Chen, “An implementation of fast-locking and wide-range 11-bit reversible SAR DLL,” IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 57, no. 6, pp. 421-425, June 2010. DOI: 10.1109/TCSII.2010.**.
[PATENTS GRANTED IN RECENT YEARS]
Year 2019 (19 in total: 3 US patents, 16 China Patents)
[1] L. Liu, A. Luo, S. Wei. Method and Device for Recording Memory Access Operation Information. American patent, US **B2, April 2019.
[2] L. Liu, Y. Wu, S. Wei. Reconfigurable Processor and Timing Control Method Thereof. American patent, US **B2, February 2019.
[3] L. Liu, Y. Wang, G. Peng, Z. Li, S. Yin, S. Wei. Method and Device for Generating Configuration Information of Dynamic Reconfigurable Processor. US **B2, January 2019.
[4] L. Liu, B. Wang, M. Zhu, A. Li, S. Yin, S. Wei. Random infection fault attack prevention method based on INS network. China Patent, ZL8, September 2018.
[5] L. Liu, M. Zhu, S. Wei. Method and system for realizing safe algorithm and decryption algorithm by means of reconfigurable processor. China Patent, ZL7, August 2019.
[6] L. Liu, M. Zhu, S. Wei. Method and system for configuring reconfigurable computation array. China Patent, ZL5, July 2019.
[7] L. Liu, M. Zhu, S. Wei. Method and system for task allocation of reconfigurable processing system. China Patent, ZL2, May 2019.
[8] L. Liu, A. Luo, S. Wei. Method, detection apparatus and system for determining processor security. China Patent, ZL3, April 2019.
[9] L. Liu, A. Luo, S. Wei. Processor safety detection method and system and detection device. China Patent, ZL3, April 2019.
[10] L. Liu, M. Zhu, S. Wei. Configuration method and system of reconfigurable calculation array. China Patent, ZL8, April 2019.
[11] L. Liu, M. Zhu, S. Wei. Data encryption method, device and system. China Patent, ZL1, April 2019.
[12] L. Liu, A. Luo, S. Wei. Method, device and device for carrying out safety detection on central processing unit CPU. China Patent, ZL8, March 2019.
[13] L. Liu, Z. Li, S. Wei. Method and device for processing irregular applications. China Patent, ZL5, March 2019.
[14] L. Liu, A. Luo, S. Wei. Processor detection method, device and system. China Patent, ZL9, March 2019.
[15] L. Liu, Y. Wu, S. Wei. Reconfigurable processor and time sequence control method thereof. China Patent, ZL7, March 2019.
[16] L. Liu, M. Zhu, Y. Wu, K. Luo, S. Yin, S. Wei. AES (Advanced Encryption Standard) encryption method and power attack resisting method based on the same. China Patent, ZL2, February 2019.
[17] L. Liu, A. Luo, S. Wei. Memory access operation information recording method and device. China Patent, ZL6, February 2019.
[18] L. Liu, G. Peng, p. Zhang, Y. Xue, S. Yin, S. Wei. Integration device based on signal detection algorithm. China Patent, ZL6, January 2019.
[19] L. Liu, C. Yang, K. Luo, Z. Li, S. Yin, S. Wei. On-chip cache prefetch mechanism which drives data memory access mode matching according to configuration information. China Patent, ZL6, January 2019.
Year 2018 (10 in total: 1 US patents, 9 China Patents in total)
[1] L. Liu, J. Zhu; X. Yang, S. Yin, S. Wei. Reconfigurable Processor and Conditional Execution Method for the Same. American patent, US **B2, October 2018.
[2] L. Liu, M. Zhu, Y. Wu, K. Luo, S. Yin, S. Wei. Diversified configuration information compression method and device. China Patent, ZL2, November 2018.
[3] L. Liu, P. Cao, M. Zhu, Y. Wu, S. Yin, S. Wei. Block cipher algorithm parallel computation-oriented reconfigurable S box circuit structure. China Patent, ZL7, September 2018.
[4] L. Liu, P. Zhang, G. Peng, Y. Xue, S. Yin, S. Wei. Signal detection method and device based on approximate solution solving of linear equation group. China Patent, ZL3, October 2018.
[5] L. Liu, H. Huang, M. Zhu, Y. Wu, S. Yin, S. Wei. Reconfigurable cryptographic processor. China Patent, ZL5, June 2018.
[6] L. Liu, M. Zhu, Y. Wu, K. Luo, S. Yin, S. Wei. Caching apparatus used for reconfigurable cipher processor. China Patent, ZL2, September 2018.
[7] L. Liu, J. Wang, J. Zhu, S. Yin, S. Wei. Control flow executing method and system based on trigger instruction structure. China Patent, ZL9, November 2018.
[8] S. Yin, B. Xu, L. Liu, S. Wei, J. Zhu. Compiler optimization method for coarse-grained reconfigurable processor. China Patent, ZL9, June 2018.
[9] S. Yin, X. Lin, L. Liu, S. Wei. Reconfigurable computation cyclic mapping optimization method. China Patent, ZL7, August 2018.
[10] B. Liu, W. Zhu, Y. Liu, P. Cao, J. Yang, B. Wang, M. Yang, L. Liu, S. Wei. Embedded reconfigurable system based on large-scale coarse granularity and processing method of system. China Patent, ZL9, February 2018.
Year 2017 (16 in total: 4 US patents, 12 China Patents)
[1] L. Liu, G. Peng, P. Zhang, Y. Xue, S. Yin, S. Wei. Signal detecting method and device. American patent, US**B2, August 2017.
[2] R. Wang, S. Wei, L. Liu, E. Tang, J. Song, S. Chan, D. Wang, J. Fang, P. Peng, S. Yin. Extending the capabilities of existing devices without making modifications to the existing devices. American patent, US**B2, September 2017.
[3] P. Cao, J.Yang, L. Shi, B. Liu, J. Yang, L.Liu and et. al. Pre-decoding analysis based configuration information cache management method and system. American patent, US**B2, April 2017.
[4] L. Shi, J.Yang, P. Cao, B. Liu, J. Yang, L.Liu and et. al. Cache structure and management method for use in implementing reconfigurable system configuration information storage. American patent, US**B2, August 2017.
[5] L. Liu, B. Wang, M. Zhu, Z. Zhou, S. Yin, S. Wei. Anti-failure injection attacking method and device for interchange of input and output of registers. China Patent, ZL7.6, October 2017.
[6] L. Liu, C. Yang, K. Luo, Z. Li, S. Yin, S. Wei. Sharing on-chip cache dividing device. China Patent, ZL3.6, September 2017.
[7] L. Liu, B. Wang, Z. Zhou, M. Zhu, S. Yin, S. Wei. Space-randomization-based fault attacking resisting method applicable to reconfigurable array framework" href="javascript:;">Space-randomization-based fault attacking resisting method applicable to reconfigurable array framework. China Patent, ZL0.0, August 2017.
[8] L. Liu, C. Yang, K. Luo, Z. Li, S. Yin, S. Wei. Sharing on-chip cache dividing device. China Patent, ZL3.6, July 2017.
[9] L. Liu, Y. Wang, G. Peng, Z. Li, S. Yin, S. Wei. Method and device for generating configuration information of dynamic reconfigurable processor. China Patent, ZL8.4, June 2017.
[10] L. Liu, J. Zhu, X. Yang, S. Yin, S. Wei. Reconfigurable processor and condition execution method thereof .China Patent, ZL6.0, February 2017.
[11] L. Liu, B. Wang, M. Zhu, Z. Zhou, S. Yin, S. Wei. Design method of randomized anti-fault-attack measures for reconfigurable array architecture. China Patent, ZL4.X, April 2017.
[12] Y. Ren, L. Liu, J. Chen, S. Yin, S. Wei. Method and system for reconstructing on-chip network topological structure. China Patent, ZL 2.7, December 2017.
[13] S. Yin, Y. Peng, D. Liu, L. Liu, S. Wei. Battery power optimization method and system based on reconfigurable arrays. China Patent, ZL9.8, September 2017.
[14] P. Cao, B. Liu, M. Yang, J. Yang, J. Xiao, W. Zhu, Y. Zhang, L.Liu and et. al. Two-dimensional data access dynamic self-adapting method based on reconfigurable technology. China Patent, ZL2.9, June 2017.
[15] B. Liu, P. Cao, D. Zhuang, W. Zhu, J. Yang, J. Xiao, J. Yang, L. Liu and et. al. Coarse-grained dynamic reconfigurable system based multi-mode data access device and method, China Patent, ZL9.6, February 2017.
[16] P. Cao, B. Liu, J. MIN, Y. DU, J. Yang, J. Xiao, J. Yang, L. Liu and et. al. Shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and control method. China Patent, ZL1.2, February 2017.
Year 2016 (17 China Patents in total)
[1] L. Liu, Y. Wang, M. Zhu. Y. Zou, J. Yang and et. al. The data transmission approach, processor and system among dynamic reconfigurable processors. China patent, ZL7.3, January 2016.
[2] L. Liu, S. Yin, L. Shi, P. Cao, J. Zhu and et. al. A method to generate configuration information in software-based approach for dynamic reconfigurable processor. China patent, ZL4.5, January 2016.
[3] L. Liu, Y. Wang, M. Zhu. Y. Zou, J. Yang and et. al. A method of array expansion in dynamic reconfigurable processing element. China patent, ZL1.5, March 2016.
[4] L. Liu, J. Zhu, S. Yin, S. Wei. A low power reconfigurable array structure and power consumption optimization technique. China patent, ZL0.6, June 2016.
[5] L. Liu, S. Cai, S. Yin, W. Zhang, S. Wei. Intelligent air-conditioner adjustment method and device based on indoor scene video streaming cognition. China patent, ZL5.1, December 2016.
[6] S. Yin, Z. Zhang, L. Liu, S. Wei. A routing approach and on-chip network router. China patent, ZL6.4, July 2016.
[7] S. Yin, L. Liu, Y. Dong, Y. Deng, S. Wei and et. al. FAT file system for two masters. China patent, ZL8.4, June 2016.
[8] S. Yin, L. Liu, Y. Dong, Y. Deng, S. Wei and et. al. Method and device for previewing streaming media. China patent, ZL8.2, December 2016.
[9] Y. Ren, L. Liu, Q. Wu, J. Han, S. Yin, S. Wei. On-chip network fault-tolerant method adopting one fourth redundant structure. China patent, ZL8.9, December 2016.
[10] S. Yin, C. Qiao, L. Liu, S. Wei. A method and system to schedule tasks based on practical battery model for wireless sensor network. China patent, ZL0.4, September 2016.
[11] S. Yin, L. Liu, Y. Dong, Y. deng, S. Wei and et. al. A method to build wireless smart USB disk. China patent, ZL3.5, August 2016.
[12] S. Yin, D. Liu, L. Liu, S. Wei. A method to optimize processor loop mapping. China patent, ZL1.X, January 2016.
[13] S. Yin, P. Ouyang, L. Liu, S. Wei. A reconfigurable apparatus for object detection based AdaBoost algorithm. China patent, ZL7.6, February 2016.
[14] S. Yin, D. Liu, L. Liu, S. Wei. A performance modeling approach of multiple parameters for reconfigurable array. China patent, ZL6.4, January 2016.
[15] S. Yin, W. Xia, P. Ouyang, L. Liu, S. Wei. A method to extract the novel robust feature for face recognition. China patent, ZL0.1, August 2016.
[16] Z. Qi, Y. Du, P. Cao, J. Yang, L. Liu and et. al. Method for hiding storage access delay in reconfigurable system. China patent, ZL9.3, March 2016.
[17] P. Cao, B. Liu, J. Hu, W. Zhu, Y. Du, Z. Qi, J. Yang, L. Liu and et. al. Controller for realizing configuration information cache update in reconfigurable system. China patent, ZL4.8, March 2016.
Year 2015 (9 China Patents in total)
[1] L. Liu, S. Yin, B. Qi, L. Shi, P. Cao and et. al. A method for describing configuration information of dynamic reconfigurable array. China patent, ZL0.5, April 2015.
[2] L. Liu, M. Zhu, Y. Wang, Y. Zou, J. Yang and et. al. A dynamic reconfigurable processor. China patent, ZL3.6, March 2015.
[3] L. Liu, Y. Liu, S. Yin, J. Song, Y. Wang and et. al. A method and apparatus to use pen and paper to write and send e-mail. China patent, ZL9.1, October 2015.
[4] L. Liu, C. Wu, W. Zhang, S. Yin, S. Wei. A method to control the air conditioner intelligently based on the user’s indoor location. China patent, ZL8.6, June 2015.
[5] M. Zhu, L. Liu, Y. Wang, X. Wang, J. Yang and et. al. A method to generate sequential configuration information for dynamic reconfigurable array. China patent, ZL4.5, March 2015.
[6] S. Yin, Z. Zhang, L. Liu, S. Wei. A method and system of scheduling for on-chip wireless link. China patent, ZL4.5, December 2015.
[7] Z. Li, L. Liu, S. Yin, M. Zhu. B. Wang and et. al. A method to extract the basic operators of encryption and decryption based on reconfiguration. China patent, ZL8.2, May 2015.
[8] S. Yin, J. Zhang, P. Ouyang, L. Liu, S. Wei. A method of object recognition based on SIFT feature. China patent, ZL9.6, November 2015.
[9] S. Yin, C. Qiao, L. Liu, S. Wei. A method and system to avoid data collision for wireless sensor network. China patent, ZL4.5, October 2015.
Year 2014(7 in total: 1 US patent, 6 China Patents)
[1] J. Song, D. Wang, L. Liu, E. Tang, S. Yin. Low power and fast application service transmission. American patent, US**B2, February 2014.
[2] L. Liu, Y. Wang, M. Zhu, B. Qi, J. Yang and et. al. A method to scheduling data stream for dynamic reconfigurable processor. China patent, ZL7.6, January, 2014.
[3] L. Liu, Y. Wang, M. Zhu, B. Qi, J. Yang and et. al. A method of scalable configuration information for dynamic reconfigurable array. China patent, ZL8.6, January 2014.
[4] L. Liu, W. Zhang, C. Wu, S. Yin, S. Wei. An indoor surveillance system based on infrared light spot movement detection. China patent, ZL8.5, September 2014.
[5] M. Zhu, L. Liu, Y. Wang, X. Wang, J. Yang and et. al. A method, cache and processor to call configuration information for dynamic reconfigurable array. China patent, ZL1.0, November 2014.
[6] S. Yin, L. Liu, Y. Dong, Y. Deng, S. Wei and et. al. A method and system to test the software for Internet applications. China patent, ZL0.9, March 2014.
[7] M. Zhu, L. Liu, Y. Wang, J. Zhu, J. Yang and et. al. A method to optimize the instruction set of dynamic reconfigurable processor. China patent, ZL3.2, April 2014.
Year 2013(14 China Patents in total)
[1] L. Liu, T. Geng, S. Yin, S. Wei. A method to map and implement motion compensation algorithm on reconfigurable processor. China patent, ZL5.3, December 2013.
[2] L. Liu, S. Yin, B. Qi, L. Shi, P. Cao and et. al. A method to execute the configuration stream hierarchically for dynamic reconfigurable processor. China patent, ZL6.2, July 2013.
[3] L. Liu, Y. Wang, M. Zhu. Y. Zou, J. Yang and et. al. An expansion approach of sub-unit in dynamic reconfigurable processor. China patent, ZL3.4, May 2013.
[4] L. Liu, Y. Wang, M. Zhu, B. Qi, J. Yang and et. al. A method to call fixed number for dynamic reconfigurable processor. China patent, ZL6.9, December 2013.
[5] L. Liu, Y. Wang, M. Zhu. Y. Zou, J. Yang and et. al. A method and apparatus to implement data interaction for dynamic reconfigurable processor. China patent, ZL1.7, May 2013.
[6] L. Liu, S. Yin, B. Qi, L. Shi, P. Cao and et. al. A method and apparatus to switch configuration information for dynamic reconfigurable array. China patent, ZL6.3, August 2013.
[7] L. Liu, M. Zhu, Y. Wang, J. Zhu, J. Yang and et. al. A dynamic reconfigurable processor. China patent, ZL7.1, December 2013.
[8] L. Liu, M. Zhu, Y. Wang, J. Zhu, J. Yang and et. al. The working mechanism of configuration stream for dynamic reconfigurable array processor. China patent, ZL1.X, December 2013.
[9] L. Liu, S. Yin, L. Shi, P. Cao, J. Zhu and et. al. An apparatus and method of data cache for dynamic reconfigurable array. China patent, ZL3.6, July 2013.
[10] L. Liu, S. Yin, B. Qi, L. Shi, P. Cao and et. al. A method to support synchronization among sub-units in dynamic reconfigurable processor. China patent, ZL6.1, March 2013.
[11] L. Liu, M. Zhu, Y. Wang, B. Qi, J. Yang and et. al. A processing approach and processor of full-connected routing structure for dynamic reconfigurable processor. China patent, ZL9.7, March 2013.
[12] Y. Wang, L. Liu, M. Zhu, B. Qi, J. yang and et. al. A method to describe the configuration information hierarchically for dynamic reconfigurable processor. China patent, ZL2.6, May 2013.
[13] Y. Wang, L. Liu, M. Zhu, B. Qi, J. Yang and et. al. A method to call immediate data for dynamic reconfigurable processor. China patent, ZL8.0, July 2013.
[14] M. Zhu, L. Liu, Y. Wang, B. QI, J. Yang and et. al. A full-connected routing structure dynamic reconfigurable processor. China patent, ZL8.2, May, 2013.