尹首一 Shouyi Yin
副教授 Associate Professor
微纳电子系副系主任 Vice Director of Institute of Microelectronics
CAD室主任 Chief of CAD Division
联系方式：
清华大学信息科学技术大楼（FIT楼）3-331室
Institute of Microelectronics,
Tsinghua University, Beijing, 100084, P. R. China
Office: Room 3-331, FIT Building
电话Phone: +86-
电子邮件Email: yinsy@tsinghua.edu.cn
个人主页Homepage: https://rapidthu.wixsite.com/home
个人简介
尹首一，1977年1月生，汉族，中共党员，清华大学微纳电子系副教授、博士生导师。他分别于2000年、2002年和2005年于清华大学获得工学学士、硕士和博士学位，2005～2007年在英国帝国理工大学从事博士后工作。现任清华大学微纳电子系副系主任、CAD技术研究室主任。 尹首一副教授研究领域包括可重构计算、神经网络计算芯片、高层次综合、SoC与嵌入式系统设计等。尹首一副教授主持承担了国家科技重大专项子课题、国家863计划项目、国家自然科学基金等10余项，发表期刊论文70余篇、国际会议论文50余篇，申请发明专利45项，授权6项，获得软件著作权5项，并领衔研究和设计了可重构多模态混合神经计算芯片（代号“Thinker”）。曾获教育部技术发明奖一等奖。
Dr. Shouyi Yin received B.S, M.S. and Ph.D. from Tsinghua University in 2000, 2002 and 2005 respectively. He has been with Imperial College London, London, U.K., as a Post doc during 2005-2007. He is currently with the Institute of Microelectronics (IME), Tsinghua University, as an Associate Professor. He is now the vice director of IME and leading the division of Computer-Aided Design. His current research interests include reconfigurable computing, neural network accelerator chip design, HLS, SoC and embedded system design. Dr. Yin has published one book, a handful of book chapters, and more than 100 journal and conference papers. He has been granted with 45 China patents with other 39 pending applications. He has led the research and implementation of reconfigurable neural network processor “Thinker”. He once won the first prize of National Technology &Invention Award.
主要研究方向（Research Interests）
1） 可重构神经网络芯片：Thinker是一款基于65nm工艺、高能效的混合神经网络处理器。它共包含两个16x16的可重构异构处理单元阵列。为了对混合类型的神经网络进行加速，处理单元可根据任务需求进行划分和重构来支持对神经网络的并行处理。为了提升能效，每个处理单元均支持不同数据位宽的适应处理。实验验证显示该处理器在200MHz的时钟下可实现409.6GOPS的峰值计算性能以及5.09TOPS/W的峰值能效比，比当前最先进的设计提升了5.2倍的能效比。
Reconfigurable Neural Network Chip: "Thinker” is an energy-efficient hybrid neural network (NN) processor fabricated using 65nm technology. It has two 16x16 reconfigurable heterogeneous processing elements (PEs) arrays. To accelerate a hybrid-NN, PE array is designed to support on demand partitioning and reconfiguration for parallel processing different NNs. To improve the energy efficiency, each PE supports bit-width adaptive computing to meet variant bit-width of different neural layers. Measurement results show that this processor achieves a peak 409.6GOPS running at 200MHz and at most 5.09TOPS/W energy efficiency. It outperforms the state-of-the-art up to 5.2X in energy efficiency.
2） 可重构云计算平台：云计算能够根据计算机和其他设备的需求，提供可共享的计算处理资源以及数据。大部分的云平台均是基于CPU和GPU来实现的，然而其功耗往往较高。我们设计了可重构的云平台系统，使用课题组自行设计实现的CHAMELEON CGRA作为处理器单元。每个CHAMELEON处理器中包含有4个8x8的可重构处理单元，并基于65nm工艺实现。我们将两个CHAMELEON芯片与FPGA共同集成在PCI-E的板卡上，并在每台服务器中插入4块板卡。弹性的管理系统用来管理一个1主4从节点的小型集群。系统的计算速度与节点数目基本呈现线性的增长关系，并且其计算能效比相较于Xeon CPU呈现出将近三个数量级的提升。
Reconfigurable Cloud Computing Platform: Cloud computing provides shared computer processing resources and data to computers and other devices on demand. Most cloud platform is based on CPUs and GPUs, whose power consumption can be very high. Here we design a reconfigurable cloud platform, which uses our CHAMELEON CGRA chip as accelerator. Each CHAMELEON chip has 4x8x8 reconfigurable PEs using 65nm technology. We integrate two CHAMELEON chips onto a FPGA-assisted PCI-E board, and insert four PCI-E boards in one server. An elastic management system is build over a five-node (1 master + 4 slaves) cluster. The computing speed shows a near-linear relationship with the number of computing nodes, and the computing efficiency is about three orders-of-magnitude better than Xeon CPU under 200MHz clock.
3） 高能效粗粒度可重构编译：粗粒度可重构结构（CGRA）是一种高性能高能效的计算方案，并且能够动态执行重构。然而，目前并没有有效的自动化设计方法及高层次综合理论来支持软件程序向CGRA结构的映射。我们的研究主要集中在针对通用CGRA结构的自动化编译映射方法，并主要针对四大挑战进行研究：程序并行度挖掘、减少访存冲突的内存管理方案、降低重构成本的配置信息压缩技术以及高能效的能耗管理方案。
Energy-Efficient Compiling for CGRA:Coarse-grained reconfigurable architecture (CGRA) is a promising solution for high-performance and high energy-efficiency computing, which can be reconfigured dynamically at runtime. However, there were no effective design automation methods and high-level synthesis (HLS) theory when mapping software applications onto CGRA architecture. Our research focuses on design automation methods for general-purpose CGRA, which mainly focuses on four major challenges on these issues:Parallelism of applications exploitation for high performance;Memory management for access conflicts reduction;Configuration context compression for reconfiguration cost reduction;Energy management for high energy-efficiency solutions.
摘选论文发表情况（Selected Publication）
Detailed in http://dblp.uni-trier.de/pers/hd/y/Yin:Shouyi
[C] Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Leibo Liu, Shaojun Wei: A 1.06-to-5.09 TOPS/W Reconfigurable Hybrid-Neural-Network Processor for Deep Learning Applications. VLSI 2017
[C] Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei: A Reconfigurable Multi-modal Neural Processor for Cognitive Intelligence Applications. ISSCC-SRP 2017
[J] Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei: Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE TVLSI 2017
[C] Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei:
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA 2017
[J] Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei:A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE CAL 2016
[J] Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei: Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual-Vdd CGRAs. IEEE TCAD 2016
[J] Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE TCAS II 2016
[J] Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei: Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE TPDS 2016
[J] Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei: Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2016
[J] Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei: A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE TVLSI 2016
[J] Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei: Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2016
[J] Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Trigger-Centric Loop Mapping on CGRAs. IEEE TVLSI 2016
[C] Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei: Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016
[J] Peng Ouyang, Shouyi Yin, Yuchi Zhang, Leibo Liu, Shaojun Wei: A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. IEEE TCAS II 2015
[J] Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu, Shaojun Wei: Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. IEEE TVLSI 2015
[J] Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei: Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. IEEE TVLSI 2015
[C] Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. CICC 2015
[C] Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: RNA: a reconfigurable architecture for hardware neural acceleration. DATE 2015
[C] Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. ICCAD 2015
[C] Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Neural approximating architecture targeting multiple application domains. ISCAS 2015
[C] Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei: Polyhedral model based mapping optimization of loop nests for CGRAs. DAC 2013