1.
Introduction

Power MOS devices have many advantages, such as high input impedance, positive temperature coefficient of on-resistance, high switching frequency and wide safe working area. However, an important question with regard to LDMOS is the disadvantage of “silicon limit” R_on,sp ∝ BV^2.5, which exists between specific on-resistance and breakdown voltage^[1–3]. In order to break the "silicon limit", domestic and foreign scholars have proposed super-junction structure, high-k technology, and field plate technology to reduce the on-resistance and retain a high blocking voltage^[4–6]. A high-k is an insulating dielectric with a relative dielectric constant greater than SiO₂ (k = 3.9). The high-k dielectric in power MOS devices can effectively increase drift district concentration, which improve the withstand voltage of the device^[7–14]. The proposed structure of the field plate not only can optimize the body electric field to enhance the breakdown voltage, but also provides a low specific on-resistance channel in the ON-state^[14].



In view of the above advantages, an ultralow specific on-resistance high-k LDMOS with vertical field plate (VFP HK LDMOS) is presented in this paper. The structure of the highly doped interface N+ layer provides a voltage withstand layer. The high-k dielectric is an assisted depletion drift region, enhanced RESURF effect. When the device is reverse-blocked, they modulate the electric field simultaneously^[15]. The device not only exhibits a higher BV and a lower R_on,sp, but also has a better figure of merit (FOM).

2.
Structure and mechanism

The high-k dielectric trench is introduced in the VFP HK LDMOS compared with the conventional LDMOS, which reduces the specific on-resistance by increasing the doping concentration in the drift region. At the same time, the heavily doped N⁺ layer provides a low-resistance channel so that the specific on-resistance of the device is further to be reduced. The introduced parallel gate provides an another current channel for the device and the gate field plate pinning in the high-k dielectric forms an electron accumulation layer near the field plate, which lowers the specific on-resistance in the ON-state.



The structure of the VFP HK LDMOS is shown in Fig. 1. Where t_p, t_k, t_n, t_s and t_sub refer to the length of the gate field plate, the height of the high-k trench, the depth of the highly doped interface N+ layer, the distance from the bottom of the high-k trench to the top of the substrate, and the depth of the substrate. L_p and L_d refer to the distance between the vertical field plate and the left side of the high-k trench and the length of the highly doped interface N+ layer. The vertical field plate creates a layer of electrons around the high-k trench to reduce the specific on-resistance in the ON-state.






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Figure1.
(Color?online) Schematic cross-section view of VFP HK LDMOS.




The high-k dielectric provides the device with a polarized charge that aids in depletion of the drift region and charge balance between the device drift region and the polarization charge to achieve a uniform surface electric field. The vertical field plate modulates the electric field to avoid premature breakdown.

3.
Simulation results and discussion

Fig. 2 shows the surface electric field, vertical electric field and vertical electric potential of VFP HK LDMOS and conventional LDMOS. Fig. 2(a) shows the horizontal electric field distribution along the surface of the two structures (y = 0.01 mm).



It can be seen from Fig. 2(a) that VFP HK LDMOS has a high and uniform surface electric field. The Con. LDMOS of the surface electric field line with the horizontal axis is significantly smaller than the area of the surface electric field surrounded by the VFP HK LDMOS structure. VFP HK LDMOS source-drain electric field peak can be controlled by the value of k and the length of the vertical field plate to avoid premature breakdown. In addition, the high depletion effect of k causes a higher doping concentration in the drift region, whereas the optimal doping concentration N_d of HKLR LDMOS is greater than that of Con. LDMOS.



The vertical electric field distribution is shown in Fig. 2(b). Under optimal conditions, L_d = 40 μm, $ {N_{
m{n^+ }}} = 1$ × 10¹⁶ cm^?3 and k = 800, VFP HK LDMOS has a higher electric field peak and a larger substrate depletion in the vertical potential distribution. Therefore, the BV of VFP HK LDMOS is improved by 61.8% when compared with the conventional structure.






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Figure2.
(Color?online) Off-state electric field distribution of Con. LDMOS and VFP HK LDMOS. (a) Lateral electric field. (b) Vertical electric field.




Fig. 3(a) depicts the transfer characteristics of four structures in a comparison chart. The high-k dielectric has a strong auxiliary depletion capacity and the addition of a highly doped interface N+ layer, together to provide a low resistance channel, which allows a drastic increase in drain current, ΔI₁, under the ON-state. When a parallel gate is introduced in the HKLR LDMOS, another path for the current is provided, reducing the on-resistance and increasing the drain current, ΔI₂. The accumulation of electrons around the high-k trench is created by the vertical field plate which can be used as the gate vertical field plate in the ON-state, thus the value of ΔI₃ is added.



Fig. 3(b) shows the comparison of on-resistance and power value FOM under the optimal concentration of the drift region. As can be seen from the figure, the drain current is increased by introducing the parallel gate and gate vertical field plate at the optimal state, while the VFP HK LDMOS has the largest drift region concentration, but the smallest than regarding the on-resistance and the maximum power value.






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Figure3.
(Color?online) (a) Four kinds of structure transfer characteristics. (b) Optimal comparison of drift region concentration, specific on-resistance and power value.




Fig. 4 shows the distribution of the electron concentration at the lower interface and the left of the high-k. It can be seen from the figure that the value of k and the length of the field plate are the main factors of electron accumulation. The electron concentration at the lower interface and the left of the VFP HK LDMOS is greater, the greater the value of k. The blue line is the electron density distribution of DT HK LDMOS. The difference between it and VFP HK LDMOS is due to the absence of vertical field plates, which reflects the super electron accumulation of the gate vertical field plates.






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Figure4.
(Color?online) (a) Electron concentration distribution at the interface of high-k trench. (b) Electron concentration distribution on the left of high-k trench.




As shown in Fig. 5(a), the VFP HK LDMOS structure decreases slowly with the increase of N_d in the drift region, and reaches the optimal value at the drift region concentration of 7.4 × 10¹⁵ cm^?3. The drift region can not be completely depleted at the conventional structure when the concentration of N_d is greater than 1.1 × 10¹⁵ cm^?3.



Fig. 5(b) shows the effect of k on BV and R_on,sp. As the value of k increased, the BV of the device first is increased, reaching saturation when the value of k reaches 800, and the R_on,sp of the device is decreased because the effect of electron accumulation is better as the value of k increased.






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Figure5.
(Color?online) Effect of parameters on the BV and R_on,sp of Con. LDMOS and VFP HK LDMOS (a) N_d and (b) k value of VFP HK LDMOS.




Fig. 6 shows the influence of BV and R_on,sp because of the length t_p of the vertical field plate and the distance L_p between the field plate and the left side of the high-k trench. It can be concluded from the Fig. that the breakdown voltage of the device first is increased and then decreased when the length of the vertical field plate is increased, while the specific on-resistance of the device decreases all the time. This is because the longer the length of the vertical field plate and the concentration of the electron accumulation layer are in order to lower than the specific on-resistance. When the vertical field plate is away from the left of the high-k trench, the breakdown voltage of the device first is increased and then decreased, and the specific on-resistance is being decreased all the time. This shows that the lower the electron accumulation at the lower interface is much larger than the electron accumulation at the left of the high-k trench, as the field plate distance L_p is high, and the L_p farther the electron accumulates farther.






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Figure6.
(Color?online) (a) Influence of t_p on VFP HK LDMOS BV and R_on,sp. (b) Influence of L_p on VFP HK LDMOS BV and R_on,sp.




Table 2 exhibits the electrical performance comparison of the VFP HK LDMOS, HKLR LDMOS, DT HK LDMOS and Con. LDMOS.

Device structure	Nd (1015 cm?3)	BV (V)	Ron,sp (mΩ·cm2) @ Vgs = 15 V	BV2/Ron,sp (MW/cm2)
VFP HK LDMOS (k = 800)	7.5	629.1	38.4	10.31
HKLR LDMOS (k = 800)[14]	3.5	649	82.8	5.09
DT HK LDMOS (lp = 2k = 800)	2	162.4	86.4	0.31
Con. LDMOS	1.1	388.9	147.5	1.02

Table2.
BV, R_on,sp, FOM = BV²/R_on,sp for the devices.



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Device structure	Nd (1015 cm?3)	BV (V)	Ron,sp (mΩ·cm2) @ Vgs = 15 V	BV2/Ron,sp (MW/cm2)
VFP HK LDMOS (k = 800)	7.5	629.1	38.4	10.31
HKLR LDMOS (k = 800)[14]	3.5	649	82.8	5.09
DT HK LDMOS (lp = 2k = 800)	2	162.4	86.4	0.31
Con. LDMOS	1.1	388.9	147.5	1.02

According to the Table 1, we can obtain that the VFP HK LDMOS achieves the maximum FOM is 10.3 MW/cm² when k is 800 and N_d is 7.5 × 10¹⁵ cm^?3, which alleviates the contradiction between the R_on,sp and BV.

Symbol	Description	Value
tp	Length of gate field plate (μm)	2
tk	Depth of high-k trench (μm)	3
k	k value of high-k dielectric	800
Ld	Length of N (μm)	Optimized
Nn+	Concentration of N (cm?3)	Optimized
tn	Thickness of N (μm)	0.5
ts	Distance from the bottom of the high-k trench to the top of the substrate (μm)	2
Lp	Distance from vertical field plate to the left side of the high-k trench (μm)	2
Nd	Concentration of drift region (cm?3)	7.4 $ times $ 1016
tsub	Thickness of substrate (μm)	80
Nsub	Concentration of substrate (cm?3)	1 $ times $ 1014

Table1.
Structure parameters used in the simulation.



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Symbol	Description	Value
tp	Length of gate field plate (μm)	2
tk	Depth of high-k trench (μm)	3
k	k value of high-k dielectric	800
Ld	Length of N (μm)	Optimized
Nn+	Concentration of N (cm?3)	Optimized
tn	Thickness of N (μm)	0.5
ts	Distance from the bottom of the high-k trench to the top of the substrate (μm)	2
Lp	Distance from vertical field plate to the left side of the high-k trench (μm)	2
Nd	Concentration of drift region (cm?3)	7.4 $ times $ 1016
tsub	Thickness of substrate (μm)	80
Nsub	Concentration of substrate (cm?3)	1 $ times $ 1014

Fig. 7 shows the trade-off between different device structures BV and R_on,sp. Although VFP HK LDMOS has similar performance to HKLR LDMOS, the proposed device VFP HK LDMOS achieves lower specific on-resistance R_on,sp under the same withstand voltage, which breaks the silicon limit and a better compromise between BV and R_{on, sp} is achieved.






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Figure7.
(Color?online) Comparison of R_on,sp among different LDMOS devices.

4.
Process steps to fabricate

VFP HK LDMOS specific process steps are shown in Fig. 8. First，it etching the silicon trench is etched as shown in Fig. 8(a), which is filled with highly doped N-type silicon material. In Fig. 8(b), the trench is recutted and the high-k dielectric is filled into the silicon trench by low pressure chemical vapor deposition (LPCVD). The surface protrusions need to be planarized by chemical mechanical polishing (CMP) when filling the material. After the high-k dielectric trench is formed in the drift region, a layer of photoresist is deposited on the surface of the device and the active region is etched to form the P-well region of the trench-type SOI LDMOS by ion implantation as shown in Fig. 8(e).



After that, a P⁺ contact region and a source/drain N⁺ region are formed. Then the P-well region , the source and drain regions are formed. SiO₂ is subsequently deposited by LPCVD to form a field oxide region after densification. The next step is to fabricate the trench gate. Etching the silicon trench followed by pre-oxidation and bleaching the oxide layer are majorly steps in forming the trench gate, which reduce etch damage on the sidewalls of the trench and also reduce interfacial defects, then heat in the gate oxide is formed by oxidation, and the thickness of the gate oxide is controlled to about 100 nm, as shown in Fig. 8(f). After gate oxide formation, the deposited electrode is next shown in Fig. 8(g). After that, the excess part is etched away, and finally the protective oxide layer is deposited and the electrode metal is led out. Finally, the VFP HK LDMOS is formed after the completion of the process being shown in Fig. 8(h).






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Figure8.
Key process steps to fabricate a prototype of VFP HK LDMOS.

5.
Conclusion

This paper presents the VFP HK LDMOS, which signi?cantly improves the tradeoff between the BV and R_on,sp. Highly doped interface N+ layer and vertical gate field plate are proposed in the high-k trench under the interface. The formation of an electron accumulation layer near the field plate at the time of ON-state reduces the specific on-resistance of the device. The introduction of a parallel gate provides another current path for the device and again reduces the specific on-resistance of the device. The horizontal deflection of the power line eventually points to the gate vertical field plate and part of the parallel gate, greatly increasing the breakdown voltage of the device. The simulation results show that the BV of the VFP HK LDMOS is 629.1 V, the R_on,sp is 38.4 mΩ·cm² and the FOM is 10.3 MW/cm². Compared with HKLR LDMOS, the R_on,sp and FOM are increased by 53.6% and 102.6%, respectively.