1.Faculty of Information Technology, Beijing University of Technology, Beijing 100124, China 2.Microelectronics Institute, Beihang University, Beijing 100191, China
Fund Project:Project supported by the National Natural Science Foundation of China (Grant Nos. 61006059, 6177402, 61901010), Beijing Natural Science Foundation, China (Grant Nos. 4143059, 4192014, 4204092), Beijing Municipal Education Committee Project, China (Grant No. KM201710005027), Postdoctoral Science Foundation of Beijing, China (Grant No. 2015ZZ-11), China Postdoctoral Science Foundation (Grant Nos. 2015M580951, 2019M650404), and Beijing Future Chip Technology High-tech Innovation Center Scientific Research Fund, China (Grant No. KYJJ2016008)
Received Date:15 February 2020
Accepted Date:09 May 2020
Available Online:13 June 2020
Published Online:05 October 2020
Abstract:As one of the primary elements in magnetoresistive random access memory (MRAM), voltage controlled magnetic anisotropy magnetic tunnel junction (VCMA-MTJ) has received wide attention due to its fast read and write speed, low power dissipation, and compatibility with standard CMOS technology. However, with the downscaling of VCMA-MTJ and the increasing of storage density of MRAM, the effect of process deviation on the characteristics of MTJ becomes more and more obvious, which even leads to Read/Write (R/W) error in VCMA-MTJ circuits. Taking into account the depth deviation of the free layer (γtf) and the depth deviation of the oxide barrier layer (γtox) in magnetron sputtering technique as well as the etching process stability factor (α) caused by the sidewall re-deposition layer in the ion beam etching process, the electrical model of VCMA-MTJ with process deviation is presented in the paper. It is shown that the VCMA-MTJ cannot achieve the effective reversal of the magnetization direction when γtf ≥ 13% and γtox ≥ 11%. The precession of magnetization direction in VCMA-MTJ also becomes instable when α ≤ 0.7. Furthermore, the electrical model of VCMA-MTJ with process deviation is also applied to the R/W circuit to study the effect of process deviation on the R/W error in the circuit. Considering the fact that all of γtf, γtox, and α follow Gauss distribution, The 3σ/μ is adopted to represent the process deviation, with using Monte Carlo simulation, where σ is the standard deviation, and μ is the average value. It is shown that the write error of the circuit goes up to 30 % with 3σ/μ of 0.05 and the voltage (Vb) of 1.15 V. At the same time, the read error of the circuit is 20% with 3σ/μ of 0.05 and driving voltage (Vdd) of 0.6 V. Both the read error rate and the write error rate of the VCMA-MTJ circuit increase as process deviation increases. It is found that the write error rate can be effectively reduced by increasing Vb and reducing the voltage pulse width (tpw). The increasing of Vdd is helpful in reducing the read error rate effectively. Our research presents a useful guideline for designing and analyzing the VCMA-MTJ and VCMA-MTJ read/write circuits. Keywords:magnetic tunnel junction/ voltage controlled magnetic anisotropy/ process deviation/ read/write circuits
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--> --> --> 1.引 言物联网、5G通信和人工智能技术的飞速发展以及大数据云时代的来临, 对计算机体系结构中随机储存器(random access memory, RAM)的速度、功耗、集成度和可靠性均提出了更高要求[1]. 对于传统的基于互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)工艺的易失性RAM而言, 随着器件特征尺寸的不断缩小, 漏电流的增加以及处理器与存储器的互连延迟都将制约存储器性能提升[2]. 为了解决上述问题, 国内外****对包括相变存储器(phase change random access memory, PCRAM)、阻变存储器(resistive random access memory, RRAM)以及自旋转移力矩磁随机存储器(spin-transfer torque magnetoresistive random access memory, STT-MRAM)和自旋轨道转矩磁随机存储器(spin–orbit torque magnetoresistive random access memory, SOT-MRAM)在内的以磁随机存储器(magnetic random access memory, MRAM)为代表的非易失性RAM进行了广泛研究[3-5]. 上述非易失性RAM使系统在断电情况下不丢失数据, 可用以消除漏电流和静态功耗, 同时采用后道工艺可减小互连延迟. 其中, STT-MRAM以其高速、小尺寸且与CMOS工艺相兼容等优点, 已进入商业化初始阶段[6-8]. 然而STT-MRAM写入数据时需要较大的写入电流, 动态功耗较高[9,10]. 不同于STT-MRAM通过改变电流来引入自旋力矩和磁场, 电压调控磁各向异性磁随机存储器(voltage controlled magnetic anisotropy magnetic random access memory, VCMA-MRAM)通过改变外加电压即电场来快速调控磁化方向, 从而有效减小由电流引起的欧姆损耗, 因此具有写入速度快且写入功耗低的显著特点, 有望成为下一代的主流非易失性存储器[11-13]. 而作为构成VCMA-MRAM基本存储单元的磁隧道结(magnetic tunnel junction, MTJ), 现已受到国内外****的广泛关注[14-16]. 近年来, 随着VCMA-MTJ理论的不断深入, 有关****基于VCMA效应建立了VCMA-MTJ的电学模型[17,18], 通过电压来调控MTJ自由层磁化方向, 从而实现数据存储. 然而随着VCMA-MTJ尺寸的不断缩小, 工艺偏差对MTJ性能的影响变得越来越严重, 甚至对VCMA-MTJ电路的读写功能产生了较大影响. 本文在充分考虑磁控溅射(magnetron sputtering)薄膜生长工艺和离子束刻蚀(ion beam etching)工艺会引入工艺偏差的情况下, 给出基于工艺偏差的VCMA-MTJ电学模型, 并研究工艺偏差对VCMA-MTJ自由层磁化方向翻转的影响. 在此基础上, 进一步研究工艺偏差对VCMA-MTJ读写电路中写错误率和读错误率的影响. 本文的研究工作对于VCMA-MTJ器件及其应用电路的设计具有重要的理论和指导意义. 2.VCMA-MTJ磁化动力学研究图1为VCMA-MTJ结构示意图, 其中氧化势垒层由氧化镁(MgO)材料构成; 参考层和自由层作为VCMA-MTJ的两个电极, 均由钴铁硼(CoFeB)材料构成. 参考层磁化方向固定不变, 当外加电压(Vb)变化时, 自由层磁化方向会发生翻转[19]. 当自由层磁化方向与参考层磁化方向平行时称为平行态(P态), 器件呈低阻特性; 当自由层磁化方向与参考层磁化方向反平行时称为反平行态(AP态), 器件呈高阻特性. 图 1 VCMA-MTJ结构示意图 Figure1. Schematic structure of the VCMA-MTJ device.
进一步地, VCMA-MTJ在P态和AP态之间的切换与Vb的大小和加载时间密切相关, 下面将结合图2给出的VCMA-MTJ磁化动力学示意图进行分析. 图 2 VCMA-MTJ的磁化动力学示意图 (a)不同电压对MTJ磁化状态能量势垒的影响; (b)Vb < VC的情况; (c)Vb > VC的情况 Figure2. Illustration of magnetization dynamics for the VCMA-MTJ device: (a) The impacts of different voltages on the energy barrier of MTJ; (b) at a relatively low voltage (Vb < VC); (c) at a high positive voltage (Vb > VC).
其中(10)式中等式右侧第二项远小于第一项, 可忽略不计, 即γtox与VC呈正比关系. 图7给出了不同γtf对VCMA-MTJ磁化状态切换的影响, 其中Vb = 1.2 V, tpw = 0.4 ns. 当γtf ≤ 12%时, MTJ自由层的磁化方向能够实现从P态到AP态的切换; 当γtf ≥ 13%时, MTJ不能实现从P态到AP态的切换. 这是因为, 从(9)式可知, 随着γtf的增加, Hk将减小, 从而导致MTJ的Heff向x-y平面偏转, 这不利于磁化方向的有效翻转. 图 7γtf对VCMA-MTJ磁化方向切换的影响, 其中Vb = 1.2 V, tpw = 0.4 ns Figure7. Effect of γtf on the magnetization direction switchingof VCMA-MTJ at Vb = 1.2 V, tpw = 0.4 ns.
图8给出了不同γtox对VCMA-MTJ磁化状态切换的影响. 当γtox ≤ 10%时, 自由层的磁化矢量能够发生翻转, VCMA-MTJ将由初始的P态切换为AP态; 当γtox ≥ 11%时, VCMA-MTJ将无法实现磁化状态的切换. 这是因为, 从(10)式可知, 当γtox较大时, 临界电压VC增大, 进而影响了自由层磁化矢量的进动, 从而导致切换错误. 图 8 不同γtox对VCMA-MTJ磁化状态切换的影响, 其中Vb = 1.1 V, tpw = 0.4 ns Figure8. Effect of γtox on magnetization direction switching of VCMA-MTJ at Vb = 1.1 V and tpw = 0.4 ns.
23.2.刻蚀工艺 -->
3.2.刻蚀工艺
离子束刻蚀技术具有刻蚀速率快、图形精度高、工艺参数可控性好等优势, 因此成为MTJ刻蚀的主流工具[29-31]. 但离子束刻蚀不可避免地会产生具有磁性的非挥发刻蚀产物, 如果沟槽深度较大或者沟槽宽度较小, 则粒子不能全部飞出槽外, 导致部分粒子附着在侧壁上, 形成再沉积层[32,33](图9). 图 9 离子束刻蚀产生侧壁再沉积层示意图 (a)刻蚀产生磁性粒子; (b)粒子聚集形成再沉积层 Figure9. Illustration of the formation of the sidewall re-deposited layer with ion beam etching: (a) Producing of magnetic particleses with etching process; (b) formation of the re-deposition layer with magnetic particleses.
图16给出了VCMA-MTJ读写电路在进行读“0”操作时的蒙特卡洛仿真波形, 其中N = 100, 3σ/μ = 0.07, Vdd = 0.8 V. 结果表明, 由于工艺误差的影响, 读错误率为2%. 图 16 VCMA-MTJ读电路的蒙特卡洛仿真波形, 其中N = 100, 3σ/μ = 0.07, Vdd = 0.8 V Figure16. Monte Carlo simulation waveform of the reading circuit of VCMA-MTJ at N = 100, 3σ/μ = 0.07, Vdd = 0.8 V