魏东^{1, 2,,},
董博晨¹,
刘亦青³
1.北京建筑大学电气与信息工程学院 北京 100044
2.北京市科学技术委员会建筑大数据智能处理方法研究北京市重点实验室 北京 100044
3.北京亚鼎智能技术有限公司 北京 100071
基金项目:北京市属高校高水平创新团队建设计划项目(IDHT20190506)，国家自然科学基金(61871020)，北京市教委科技计划重点项目(KZ201810016019)

详细信息

作者简介:魏东：女，1968年生，教授，研究方向为人工神经网络优化计算
董博晨：男，1995年生，硕士，研究方向为神经网络芯片设计
刘亦青：男，1987年生，硕士，研究方向为控制科学与工程

通讯作者:魏东　weidong@bucea.edu.cn

中图分类号:TN911.73; TP183

计量

文章访问数:379
HTML全文浏览量:138
PDF下载量:89
被引次数:0

出版历程

收稿日期:2020-03-24
修回日期:2020-09-23
网络出版日期:2020-12-09
刊出日期:2021-07-10

Design and Hardware Implementation of Image Recognition System Based on Improved Neural Network

Dong WEI^{1, 2,,},
Bochen DONG¹,
Yiqing LIU³
1. School of Electrical and Information Engineering, Beijing University of Civil Engineering and Architecture, Beijing 100044, China
2. Beijing Key Laboratory of Intelligent Processing for Building Big Data, Beijing Municipal Science and Technology Commission, Beijing 100044, China
3. Beijing Yading Intelligent Technology Limited Company, Beijing 100071, China
Funds:The High Level Innovation Team Construction Project of Beijing Municipal Universities (IDHT20190506), The National Natural Science Foundation of China (61871020), The Key Science and Technology Plan Project of Beijing Municipal Education Commission of China (KZ201810016019)


摘要
摘要:针对现有图像识别系统大多采用软件实现，无法利用神经网络并行计算能力的问题。该文提出一套基于FPGA的改进RBF神经网络硬件化图像识别系统，将乘法运算改为加法运算解决了神经网络计算复杂不便于硬件化的问题，并且提出一种基于位比较的排序电路解决了大量数据的快速排序问题，以此为基础开发了多目标图像识别应用系统。系统特征提取部分采用FPGA实现，图像识别部分采用ASIC电路实现。实验结果表明，该文所提出的改进RBF神经网络算法平均识别时间较LeNet-5, AlexNet和VGG16缩短50%；所开发的硬件系统完成对10000张样本图片识别的时间为165 μs，对比于DSP芯片系统所需426.6 μs，减少了60%左右。
关键词:FPGA/
ASIC电路/
RBF神经网络/
图像识别系统
Abstract:To solve the problem that most existing image recognition systems are implemented in software which can not utilize the parallel computing power of neural networks, this paper proposes a FPGA image recognition system based on improved RBF neural network hardware. The multiplication operation in the neural networks is complex and inconvenient for hardware implementation. Furthermore, a sort circuit based on bit comparison is designed to solve the problem of fast sorting of a large number of data. Then, a multi-target image recognition application system is developed. The feature extraction part in the developed system is implemented by FPGA, and the image recognition part is implemented by ASIC circuit. The experimental results show that the average recognition time of the improved RBF neural network algorithm proposed is 50% shorter than that of LeNet-5, AlexNet and VGG16, and the time for the developed hardware system to recognize 10000 sample pictures is 165μs, which is reduced by about 60% compared with 426.6μs required by a DSP chip system.
Key words:FPGA/
ASIC circuit/
RBF neural networks/
Image recognition system



PDF全文下载地址:

https://jeit.ac.cn/article/exportPdf?id=78675f08-5f9c-4d80-9caa-c562ed0d538a