中国电子科技集团公司第五十四研究所 石家庄 050080
详细信息
作者简介:胡东伟：男，1980年生，高级工程师，研究方向为无线通信理论和数字大规模集成电路设计
通讯作者:胡东伟 hudw1980@sina.com
中图分类号:TN915计量
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被引次数:0
出版历程
收稿日期:2020-01-13
修回日期:2020-07-11
网络出版日期:2020-07-24
刊出日期:2021-04-20
On the Implementation of 5G LDPC Decoder
Dongwei HU,54th Institute of CETC, Shijiazhuang 050080, China
摘要
摘要:该文介绍了5G标准中LDPC码的特点，比较分析了各种译码算法的性能，提出了译码器实现的总体架构：将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形，为译码器的主体；低信噪比译码器主要针对低码率、低信噪比下的高性能译码，处理一些极限情形下的通信，对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践，给出了FPGA综合结果和吞吐率分析结果。
关键词:5G移动通信/
低密度奇偶校验码/
译码器/
FPGA
Abstract:This paper focuses on the Low-Density-Parity-Check (LDPC) decoder for 5G New Radio (NR) specification. After introducing the characteristics of the LDPC code in 5G NR, the performance of different decoding algorithms are compared, and then the overall architecture of the decoder is proposed. In the proposed architecture, the decoder is divided into high-speed decoder and high-performance decoder. The high-speed decoder is intended for high-rate and high throughput decoding, while the high-performance decoder is used for low-rate decoding under low Signal-to-Noise-Ratio (SNR) scenarios, which is for communications under extremely bad situations, and does not need a high throughput. The design is implemented on Field Programmable Gate Array (FPGA) and the results are shown.
Key words:5G Mobile Communications/
LDPC/
Decoder/
Field Programmable Gate Array (FPGA)
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