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K波段低噪声集成片上CMOS接收前端设计

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K波段低噪声集成片上CMOS接收前端设计
A CMOS Receiver Front-End for K-Band Low-Noise System-on-Chip
投稿时间：2016-07-07
DOI：10.15918/j.tbit1001-0645.2017.03.012
中文关键词:K波段接收前端低噪声放大器下变频混频器CMOS
English Keywords:K-bandreceiver front-endlow noise amplifierdown-conversion mixerCMOS
基金项目:国家自然科学基金资助项目（61301006，61271113）
作者单位
李潇然北京理工大学 信息与电子学院, 北京 100081
仲顺安北京理工大学 信息与电子学院, 北京 100081
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中文摘要:
基于TSMC 90nm CMOS工艺，设计实现K波段片上集成CMOS接收前端。接收前端由两级差分共源共栅结构低噪声放大器、双平衡吉尔伯特单元结构下变频混频器组成。射频输入、本振输入以及模块间采用片上巴伦进行匹配。测试结果表明，在射频输入频率23.2GHz时，转换增益为27.6dB，噪声系数为3.8dB，端口隔离性能良好，在电源电压为1.2V下，功耗为35mW，芯片面积为1.45×0.60mm2。
English Summary:
The Si-base technology can help SOC (system-on-chip) to achieve smaller size, lower cost and low power consumption. In this paper, a fully integrated K-band CMOS receiver front-end was designed based on TSMC 90nm CMOS technology. The receiver front-end consisted of a 2-stage differential cascode low noise amplifier (LNA) and a double balanced Gilbert cell down-conversion mixer. The RF input, LO input and between the LNA and mixer were matched with on-chip transformer Balun. Measurement results show that, when RF is at 23.2GHz, the conversion gain can reach 27.6dB, the noise figure just is 3.8dB, and a high isolation can be got. The receiver chip consumes 35mW with a 1.2V power supply, and only occupies a chip area of 1.45×0.60mm2.
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相关话题/信息 北京理工大学 电子 北京 设计

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