Verilog HDL 是应用最为广泛的C语言基础上发展起来的一种硬件描述语言（Hardware Descripion Language）。它较VHDL（Very high Speed Integrated Circuit HDL）更加简单、规范、而且易学。Verilog HDL 的工业标准化，顺便应微电子技术发展的历史潮流，其已经在深亚微米百万门级的复杂数字逻辑电路设计及系统设计方面，显示了强大的能力。 Verilog HDL用于从开关级到算法级的多个抽象设计层次数字设计的建模。该语言提供一套功能强大的原语集，并提供了丰富的结构。这些结构不仅用于硬件的并发行为的建模，而且用于硬件的时序特性和结构建模。Verilog HDL 语言使用简便，功能强大。 对从事微电子技术领域研究、设计的研究生应尽快熟练掌握这种新的设计方法，使我国在复杂数字电路设计及系统设计的竞争中，逐步缩小与世界工业发达国家的差距。

VerilogHDL is the most popular hardware description language based on C language. It is more simple, powerful and easy than VHDL (Very high Speed Integrated Circuit HDL). Verilog HDL has become a industry standard and showed its power in system design of submicron million-scale complex digital logic circuit. Verylog HDL can be used in multi-layer abstract pattern construction, from “switch” layer to “algorithmic” layer. It has a set of design mechanism, providing powerful language collection and abundant constructions. These constructions con not only be used to design pattern on hardware intercurrent behavior, but also on hardware scheduling pattern design. After all, Verylog HDL is a very powerful tool.Taking the course gives those who in the field of micro electronic field an opportunity to master the language quickly, and give them the ability to design complex digital circuit and system.