李靖 邮箱：lijing686@uestc.edu.cn
电话：
系别：集成电路与系统系
职称：副教授
教师个人主页：


教师简介
教育背景
2017.09-2018.08 代尔夫特理工大学，访问****
2009.09－2014.12 电子科技大学，微电子学与固体电子学专业，博士学位
2005.09－2009.07 电子科技大学，微电子技术专业，学士学位

工作履历
2014.02 - 2021.07 电子科技大学，讲师
2021.08 - 至今 电子科技大学，副教授

学术兼职
IEEE member；
第14届IEEE APCCAS TPC member；
IEEE TCAS-II、IEEE T-VLSI、IEEE OJCS、IEEE ASICON等期刊和会议审稿人。


荣誉奖励
2020年度集成电路与系统一支部“优秀党员”；
2020.11，电子科技大学第九届教学成果奖一等奖，电子科技大学，排名3；
2020.11，电子科技大学第九届教学成果奖三等奖，电子科技大学，排名2；
2019.12，2019年“集成电路工程项目实训优秀校内指导老师”;
2017.08，“华为杯”第十二届中国研究生电子设计竞赛全国一等奖，优秀指导教师;
2017.06，第一届全国大学生集成电路创新创业大赛全国二等奖，优秀指导教师;
2016.12，电子科技大学微电子与固体电子学院，教学优秀奖;
2014年，博士研究生国家奖学金;
2014年，唐立新奖学金。

科学研究
研究方向：
数模混合集成电路和生物医学集成电路，包括超高速/低功耗/高精度ADC、超声成像专用集成电路、心电信号采集专用集成电路、高精度全CMOS温度传感器等。
学术成果:
先后承担和参与了自然科学基金、总装预研、国防科工局重点、四川省重点研发等省部级项目10余项。在IEEE集成电路领域顶级会议CICC、VLSI和顶级期刊TCAS-I、TCAS-II等国内外期刊和会议上发表/合作发表论文40余篇，申请发明专利近50项，授权42项。IEEE TCAS-II、IEEE T-VLSI、IEEE OJCS、IEEE ASICON等期刊和会议审稿人, 第14届IEEE APCCAS TPC member。
文章列表：
Q. Zhang, J. Li, Z. Zhang, K. Wu, N. Ning and Q. Yu, "A13b-ENOB Third-Order Noise-Shaping SAR ADC using a Hybrid Error-Control Structure," 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. 1-2, doi: 10.1109/CICC51472.2021.**.
J. Li, Y. Lin, N. Ning and Q. Yu, "A +0.44°C/?0.4°C Inaccuracy Temperature Sensor With Multi-Threshold MOSFET-Based Sensing Element and CMOS Thyristor-Based VCO," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 1102-1113, March 2021.doi: 10.1109/TCSI.2020.**, WOS:0006**（通讯：李靖）
Q. Zhang, N. Ning, J. Li, Q. Yu, K. Wu and Z. Zhang, "A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 227-231, Jan. 2021, doi: 10.1109/TVLSI.2020.**.（通讯：宁宁，李靖）
Q. Zhang, N. Ning, J. Li, Q. Yu, Z. Zhang and K. Wu, "A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4396-4408, Dec. 2020, doi: 10.1109/TCSI.2020.**. （通讯：宁宁，李靖）
Z. Zhang, Q. Yu, J. Li, X. -Z. Wang and N. Ning, "A 12-Bit Dynamic Tracking Algorithm-Based SAR ADC With Real-Time QRS Detection," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 2923-2933, Sept. 2020, doi: 10.1109/TCSI.2020.**. （通讯：李靖）
Jing Li, Yuyu Lin, Siyuan Ye, Kejun Wu, Ning Ning, Qi Yu, A CMOS-Thyristor Based Temperature Sensor With +0.37℃/-0.32℃ Inaccuracy, Micromachines, 11(124), pp.1-12, Jan 2020
Zhong Zhang, Qi Yu, Qihui Zhang, Ning Ning and Jing Li, A Kalman filtering based adaptive threshold algorithm for QRS complex detection，BIOMEDICAL SIGNAL PROCESSING AND CONTROL, Volume 58, April 2020（通讯：宁宁）
Jian Luo, Yang Liu, Jing Li, et.al, A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC, IEEE Transactions on Circuits and Systems I: Regular Papers, 67(4)，pp.1136-1148，2020, 04. （通讯：李靖，宁宁）
Z. Zhang, J. Li, Q. -H. Zhang, N. Ning and Q. Yu, "A 10-Bit Fully-Predictive ADC with Code-Recombination Algorithm in Transducing Sensor Node Signals," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.**.
Jing Li, Zhao Chen, Mingliang Tan, et.al, A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes，2019 Symposium on VLSI Circuits，2019.06.
Jing Li, Xin Ye, Jian Luo, et.al, A Full-band Timing Mismatch Calibration Technique in Time-Interleaved ADCs，Journal of Circuits, Systems, and Computers，28(6)，pp **-（1-14），2019.06.
Jian Luo, Jing Li, et.al, A Bandwidth Mismatch Optimization Technique in Time Interleaved ADCs，Journal of Circuits, Systems, and Computers，28(6)，pp **-（1-14），2019.06.
Jian Luo, Jing Li, et.al, A Low Voltage 10-bit Non-binary 2bpercycle Time and Voltage Based SAR ADC，IEEE International Symposium on Circuits and Systems(ISCAS)，2019.05.
Qihui Zhang, Jing Li, et.al, A Low-Power and Area-Efficient 14-bit SAR ADC with Hybrid CDAC for Array Sensors, IEEE International Symposium on Circuits and Systems(ISCAS)，2019.05.
Jian Luo, Jing Li, et.al, A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS，IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS，pp.1980-1988, 2018.10.
Zhong Zhang, Jing Li, et.al, A Dynamic Tracking Algorithm Based SAR ADC in Bio-related Applications，IEEE Access，pp. 62166-62173，2018.10.
Jian Luo, Jing Li, et.al, The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction，IEEE Access，pp.7037-7043，2018,06.
Jing Li, Jian Luo, Yongfeng Ding, and Ning Ning. A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter, 2018 IEEE Asia Pacific Conference on Circuits and System, Chengdu, Oct, 2018
Jing Li, Pengfei Zhou, Yuanbin Hu, Zhaochi Wang, Yi Wei, Chengze Li, Kejun Wu and Ning Ning. 0.1°C accuracy ICO temperature sensor with segmentation algorithm. Electronics Letters, 2018, 54(11), pp.686-687.
Jing Li, Huigui Wu, Ning Ning, Shuangyi Wu, Rui Guo. An improved switched-emitter-follower for high-resolution GS/s-rate track-and-hold amplifiers. 2016 IEEE International Nanoelectronics Conference (INEC), Chengdu, May, 2016
Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu. A digital timing mismatch calibration technique in time-interleaved ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(7):486-490
Jing Li, Ning Ning, Ling Du, Qi Yu, and Yang Liu. The impact of gate leakage current on PLL in 65 nm technology: analysis and optimization[J]. Journal of Semiconductor Technology and Science, 2012, 12(1):99-105
Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. Digital background calibration for timing skew in time-interleaved ADC[J]. Journal of Circuits, Systems, and Computers, 2014, 23(8):**(1-13)
Jing Li, Yang Liu, Shuangyi Wu, Chang Yang, Ning Ning, Qi Yu. Design of a fast locking DLL with background timing skew calibration[J]. Nanoscience and Nanotechnology Letters, 2014, 6(12):1068-1074
Jing Li, Ning Ning, Yong Hu, Kejun Wu. A Low-jitter Low-area PLL with Process-independent Bandwidth[C]. 2012 IEEE International Conference on Solid-State and Integrated Circuit Technology, Xi’an, 2012, 1-3
Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. A background jitter optimization method for PLL based on time-to-digital converter[C]. 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014
Jing Li, Yang Liu, Hao Liu, Shuangyi Wu, Ning Ning and Qi Yu. A timing skew calibration scheme in Time-interleaved ADC[J]. Journal of Computer and Communications, 2013, 1:37-40
Ning Ning, Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. Multiscaling coeffcients technique for gain error background calibration in pipelined ADC[J]. Journal of Circuits, Systems, and Computers, 2014, 23(3):**(1-12)
Ning Ning, Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. Multi scaling coefficients technique for noisy signal based gain error background calibration[C], 2012 IEEE International Conference on Electron Devices and Solid-State Circuits, Bangkok, 2012
Ning Ning, Yong Hu, Jing Li, Chang Yang, Shuangyi Wu, Qi Yu. Design of a four phase 25% duty cycle DLL with calibration[C], 2013 IEEE International Conference on Electron Devices and Solid-State Circuits, Hongkong, 2013
Qi Yu, Chang Yang, Jing Li, Shuangyi Wu, Ning Ning. Design of a high resolution multi-phase clock generato rbased on DLL[C], 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014
李靖，吴霜毅，宁宁，于奇. 一种时间交织ADC采样时间失配的数字校正技术[C]. 2013年全国博士生学术论坛-电子薄膜与集成器件，成都，2013，100-108
宁宁，倪春晓，李靖，宋文青，朱波，徐双恒，郑杰. 高性能AB类折叠共源共栅CMOS放大器设计[J].微电子学,2013,43(3):333-336
宋文青，于奇，朱波，李靖，倪春晓. 一种具有采样保持功能的开关电容积分器[J]. 微电子学与计算机,2013,30(3):51-54

学生培养:
2020.10，指导学生参加“华为杯”第三届中国研究生创“芯”大赛，荣获全国三等奖；
2017.08，指导学生参加“华为杯”第十二届中国研究生电子设计竞赛，荣获全国一等奖；
2017.06，指导学生参加第一届全国大学生集成电路创新创业大赛，荣获全国二等奖；
协助指导毕业硕士研究生10余名，均毕业就职于华为海思、芯原微电子、汇顶、联发科等国内外知名企业。


主讲课程
主讲课程
《集成电路原理》，IC综合实验2（IC设计）