虞亚军--教学副教授 个人主页
虞亚军博士长期从事数字信号处理及大规模集成电路研究。主要工作包括高性能低功耗数字滤波器设计、优化与实现，以及数字信号处理在通讯医学领域的应用等。在顶尖国际期刊发表论文30余篇，担任多家国际期刊编委，并客座主编数字信号处理领域特刊一期。现为美国电子电气工程院高级会员，电路与系统协会数字信号处理技术委员会委员。

教育经历 2004年 ? 新加坡国立大学? 电气与计算机系 ?博士学位
1997年 ? 浙江大学 ? 生物医学及仪器工程学系 ?硕士学位
1994年 ? 浙江大学 ? 生物医学及仪器工程学系 ?学士学位
工作经历 2016.08 - 现在：中国南方科技大学，电子与电气工程系，副教授
2005.12?- 2016.02，新加坡南洋理工大学，电子与电气工程学院，助理教授
2009.07，澳大利亚科廷大学，数学与统计系，访问教授
2004.01?- 2005.11，新加坡南洋理工大学，淡马锡实验室，研究员
2002.10?- 2003.07，香港科技大学，应用数学系，访问****
2002.06?- 2002.09，芬兰坦佩雷技术大学，电子媒体研究院，访问****
1998.05?- 2004.01，新加坡国立大学，电气与计算机系，研究工程师
1997.07?-?1998.04，浙江大学，生物医学工程及仪器系，助教
研究简介 主要从事数字信号处理，滤波器设计，及超大规模集成电路数字系统设计的研究。在国际学术期刊发表SCI论文30多篇，国际会议论文30多篇。现为IEEE Circuits & Systems Society, 数字信号处理技术委员会委员。
研究领域：
数字信号处理，滤波器设计
超大规模集成电路数字系统设计
所获荣誉 2011年，学生叶文彬获亚太研究生电子和微电子会议论文(PrimeAsia 2011)银叶奖。获奖论文为：叶文彬和虞亚军“An algorithm for the design of low power linear phase FIR filters”。银叶奖表彰会议首20%的优秀论文。
2009年，学生施栋获得IEEE Circuits & Systems Singapore Chapter优秀研究生奖。
1997年，获得浙江省科技进步三等奖。这一奖项是表彰三年内浙江省在科学技术相关领域内取得的成就的最高奖项。该奖项是根据相关研究的总体水准，对科技进步的促进作用，以及对社会和经济的影响力来评选的。
代表文章 1.X. Lou, P. K. Meher, Y. J. Yu and W. B. Ye, “Novel Structure for Area-Energy-Efficient Implementation of FIR Filter”, IEEE Transactions on Circuits and Systems II, vol. 64, no. 10, pp. 1212-1216, Oct. 2017.
2.W. B. Ye, X. Lou, and Y. J. Yu, “Design of Low Power Multiplierless Linear-Phase FIR Filters”,IEEE Access, vol. 5, pp. 23466-23472, 2017.
3.X. Lou,?Y. J. Yu?and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”,?IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems,?vol. 36, no. 2, pp. 313 – 324, Feb. 2017.
4.X. Lou,?Y. J. Yu?and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”,?IEEE Trans. Circuits, Syst. I,vol. 63, no. 10, pp. 1701 – 1703, Oct. 2016
5.R. Fan,?Y. J. Yu?and Y. L. Guan, “Improved Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”,?IET Communications,?vol. 10, iss. 8, pp. 969-974, Aug. 2016.
6.W. B. Ye and?Y. J. Yu, “Greedy Algorithm for the Design of Linear-Phase FIR Filter with Sparse Coefficients”,?Circuits Systems and Signal Processing,?vol. 35, no. 4, pp. 1427-1436, April 2016.
7.X. Lou,?Y. J. Yu?and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”,?IEEE Trans. Circuits, Syst. I., vol. 62, no. 11, pp. 2695-2705, Nov. 2015.
8.R. Fan,?Y. J. Yu?and Y. L. Guan, “Generalization of Orthogonal Frequency Division Multiplexing with Index Modulation”,?IEEE Trans. Wireless Communications, vol. 14, no. 10, pp. 5350-5359, Oct. 2015.?
9.W. B. Ye and?Y. J. Yu, “Two-step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters”,?IEEE Trans. Circuits, Syst. I., vol. 62, no. 5, pp. 1279-1287, May 2015.?(ISCAS’14?推选最佳论文，受邀提交IEEE TCAS-I?特刊文章。)
10.X. Lou,?Y. J. Yu?and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”,?IEEE Trans. Circuits, Syst. I., vol. 62, no. 3, pp. 863-872, March 2015.
11.W. B. Ye, and?Y. J. Yu, “Bit-level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique”,?IEEE Trans. Circuits, Syst. I., vol. 61, no. 11, pp. 3206-3215, Nov. 2014.
12.W. J. Xu,?Y. J. Yu, and H. Johansson, “Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters”,?IEEE Trans. Circuits, Syst. I., vol. 61, no. 3, pp. 764-777, March 2014.
13.W. B. Ye, and?Y. J. Yu, “Single Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm”,?IEEE Trans. Circuits, Syst. I., vol. 60, no. 11, pp. 2987-2997, Nov. 2013.?(ISCAS’12?推选最佳论文，受邀提交IEEE TCAS-I?特刊文章。)
14.Y. J. Yu, and W. J. Xu, “Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters”,?IEEE Trans. Circuits, Syst. II., vol. 60, no. 8, pp. 522-526, Aug. 2013.
15.S. Y. Park, and?Y. J. Yu, “Fixed-Point Analysis and Parameter Selections of MSR-CORDIC with Applications to FFT Designs”,?IEEE Trans. Signal Processing,?vol. 60, no. 12, pp.6245-6256, Dec. 2012.
16.Y. J. Yu, and W. J. Xu, “Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay”,?IEEE Trans. Signal Processing, vol. 60, no. 1, pp.100-111, Jan. 2012.
17.D. Shi, and?Y. J. Yu, “Design of Discrete-valued Linear Phase FIR Filters in Cascade Form”,?IEEE Trans. Circuits, Syst. I. vol. 58, no. 7, pp.1627-1636, July 2011.?(ISCAS’10?推选最佳论文，受邀提交IEEE TCAS-I?特刊文章。)
18.R. Bregovic,?Y. J. Yu, T. Saram?ki, and Y. C. Lim, “Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion Utilizing the Coefficient Symmetry”,?IEEE Trans. Circuits, Syst. I.?vol. 58, no. 3, pp. 548-561, Mar. 2011.?
19.D. Shi, and?Y. J. Yu, “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”,?IEEE Trans. Circuits, Syst. I.?vol. 58, no. 1, pp. 126-136, Jan. 2011.
20.R. Bregovic,?Y. J. Yu, A. Viholainen and Y. C. Lim, “Implementation of Linear-Phase FIR Nearly Perfect-Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry”,?IEEE Trans. Circuits, Syst. I.?vol. 57, no. 1, pp. 139-151, Jan. 2010.
21.Y. J. Yu, D. Shi, and Y. C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space”,?IEEE Trans. Circuits, Syst. I,?vol. 56, no. 12, pp. 2621-2633, Dec. 2009.
22.Y. J. Yu, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR filters with Sharp Transition Band”,?IEEE Trans.?Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.
23.Y. J. Yu?and Y. C. Lim, “Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming”,?IEEE Trans. Circuits, Syst. I,?vol. 54, no. 10, pp. 2330-2338, Oct. 2007.
代表著作与论文 1.L. Wanhammar, and?Y. J. Yu, “Digital Filter Structures and Their Implementation”?Academic Press Library in Signal Processing: Volume 1: Signal Processing Theory and Machine Learning, (Editor-in-Chief: Sergios Theodoridis and Rama Chellappa, Publisher: Academic Press), 2013.
招聘信息 本课题组正在招聘具有信息工程及/或超大规模集成电路设计背景的研究助理, 有意应聘者请随时与我联系了解详情。
联系方式 电子邮箱：yuyj@sustech.edu.cn