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Design of CMOS active pixels based on finger-shaped PPD

本站小编 Free考研考试/2022-01-01



1.
Introduction




As a key technology for recording image information, solid-state image sensors have received much attention. Solid-state image sensors are divided into charge coupled device (CCD) image sensors and complementary metal oxide semiconductor image sensors (CISs). Early on, CISs had problems such as high noise, low sensitivity, and severe image lag due to process level limitations, which made their application range narrower than CCD[1]. With the continuous development of CMOS technology, CIS has gradually overtaken CCD image sensor[2, 3]. At present, CISs are widely used in consumer electronics, biomedicine, security monitoring, automotive electronics, and industrial imaging due to their low power consumption, low cost, and easy integration[4-6]. However, with the growing requirements of various application, especially in the high-end imaging field, the requirements for wide dynamic range (DR) have become the main difficulties and challenges to be overcome at present[7-9].



DR is an important indicator of CIS, which reflects the range of the maximum light intensity signal and the minimum light intensity signal that CIS can detect[10]. DR can be calculated as:









$$
m{DR} = 20lg frac{{{N_{{
m{FWC}}}}}}{{{N_{{
m{noise}}}}}},$$

(1)



where NFWC and Nnoise are the full well capacity (FWC) and read noise, respectively. According to Eq. (1), the FWC is one of the decisive factors in determining the CIS DR. The linear dynamic range can be further improved by increasing the FWC. The FWC can be increased by enlarging the PPD photosensitive area. However, the ratio of PN junction contact area to PPD volume in the traditional cube pinned photodiode (PPD) is relatively low, which will cause the pinned voltage Vpin to be relatively high. A large Vpin will cause incomplete transfer of photo-generated electrons in the PPD, resulting in image lag[11-13] and increasing charge transfer noise[14], which ultimately limits the expansion of the dynamic range. Therefore, a special finger-shaped PPD structure is designed in this paper to ensure a large FWC and PPD complete depletion, thereby effectively improving the linear dynamic range of the CIS. Meanwhile, to reduce the deviation between TCAD simulation results and chip measurement results, the process calibration was performed by using secondary ion mass spectroscopy (SIMS) data[15] and TCAD tools. The device simulations in this paper are based on process calibration.




2.
Theory analysis of PPD design




To enhance the longitudinal electric field strength of the PPD and achieve a deeper depletion region depth, four times N-type ion implantations as shown in Fig. 1 are used to form the N buried layer of the PPD. TG and FD represent transfer gate and floating diffusion node, respectively. The four times N-type ion implantations are completed by self-alignment technology[16], and the implantation dose and implantation energy determine the charge transfer speed, charge transfer efficiency, and full well capacity in the pixel. Therefore, the optimal N-type ion implantation dose and implantation energy must be obtained through TCAD device simulation according to specific requirements and CMOS processes when designing a pixel.






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Figure1.
N buried layer structure of PPD.




For a traditional large-area cube-shaped PPD, it is difficult to achieve full depletion of the PPD region even with four times N-type ion implantations. Fig. 2 is the TCAD two-dimensional simulation result using the traditional cubic PPD structure, where the white curve is the depletion region boundary. It can be seen from Fig. 2 that the central area of the PPD cannot always be fully depleted, which will cause incomplete photo-generated charges transfer and image lag. There is a certain fluctuation in the amount of charges in the undepleted region, which will deteriorate the noise performance of the CIS and eventually affect the imaging quality of the CIS.






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Figure2.
(Color online) 2D TCAD simulation of depletion region in traditional cubic PPD.




In this paper, the finger-shaped PPD structure is used to solve the problem that the large-sized cube-shaped PPD is difficult to achieve full depletion. Fig. 3 shows the three-finger PPD structure used in this paper and its top view. The finger-shaped PPD design can increase the lateral electric field strength of the PPD, thereby ensuring the large-sized PPDs are fully depleted. Moreover, compared with the traditional cube-shaped PPD structure, this structure increases the contact area of the PN junction (including capacitors C1, C2, C3, and C4), thereby increasing the unit-area capacitance of the PPD[17, 18]. According to the expression of FWC:






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Figure3.
(Color online) The finger-shaped PPD and its top view.










$${N_{{
m{FWC}}}} = {A_{{
m{PPD}}}} {C_{{
m{PPD}}}} left( {{V_{{
m{pin}}}} - {V_{{
m{int}}}}}
ight)/{{q}},$$

(2)



where APPD is the total area of PPD, CPPD is the unit-area capacitance of PPD, Vpin and Vint are the pinned voltage of PPD and the initial voltage value when the pixel is saturated, respectively. It can be obtained from this formula that when the unit-area capacitance of the PPD increases, the full well capacity of the CMOS image sensor is increased, thereby improving the dynamic range of the CIS.



Although the TCAD 2D simulation results have certain errors with the actual chip measurement results, the corresponding trends and effects are consistent. In addition, the process calibration by SIMS can greatly improve the consistency between the simulation results and the measurement results. In this paper, a 2D simulation of the finger-shaped PPD is performed, and the following processing is performed:



a) When designing ion implantation conditions of finger-shaped PPD, the depletion region range, FWC and Vpin of a single-finger PPD are first confirmed. Then, the corresponding parameters of the entire finger-shaped structure are estimated.



b) When designing the width and spacing of a finger-shaped PPD, the depletion region range, FWC and Vpin are calculated and evaluated by two adjacent single-finger PPDs.



The following simulations and designs are based on the above simulation flow and process calibration.




3.
Schematic design of the high FWC CMOS active pixel





3.1
Basic process design




After several TCAD simulation experiments, this paper pre-determined a basic version of ion implantation process conditions. The four graphs in Fig. 4 are the potential distribution diagrams of finger-shaped PPD in the initial stage, after light irradiation, during transfer, and after transfer (based on the above basic process conditions). Figs. 5(a) and 5(b) are the potential distributions during the charge transfer process and the potential curve along the charge transfer path under the basic process conditions, respectively. It can be seen that there are no potential barriers or potential wells on the charge transfer path, and the signal charges can be transferred from the PPD to the floating diffusion node (FD) without hindrance, thereby achieving the complete transfer of signal charges.






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Figure4.
(Color online) Under the basic ion implantation process conditions, the potential distribution in (a) initial phase, (b) after illumination phase, (c) transfer phase, (d) post-transition phase.






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Figure5.
(Color online) Under the basic ion implantation process conditions: (a) the potential distribution in transfer phase, (b) the potential curve on the charge transfer path.





3.2
Finger-shaped PPD width simulation design




In a pixel, the pinned voltage Vpin of the PPD determines the ability of the PPD to store charge and the rate of charge transfer. A larger Vpin means a larger FWC of the PPD and a slower charge transfer rate. Vpin can be expressed as[19]:









$${V_{{
m{pin}}}} = frac{{q{N_{
m{D}}}{d^2}}}{{2varepsilon }} + frac{{{E_{
m{g}}}}}{{2q}} - frac{{kT}}{q}{
m{ln }} {frac{{{N_{
m{C}}}}}{{{N_{
m{D}}}}}} ,$$

(3)



where ND is the doping concentration of the N-type region, NC is the effective state density of the conduction band, d is the depth of the PPD (the width of the short side), ε is the dielectric constant of the silicon material, Eg is the band gap width, k is the Boltzmann constant, and T is the absolute temperature. It can be seen from this formula that Vpin is mainly related to the depth of finger-shaped PPD. Therefore, based on the above-mentioned basic process conditions, this paper uses 0.1 μm as the step size to perform device simulation on different finger-shaped PPDs with widths between 0.6 and 1.0 μm. The simulation results are shown in Figs. 6(a)–6(e). Table 1 shows the Vpin, NFWC, and depletion region depth W of PPDs with different finger widths d.






d (μm)0.60.70.80.91.0
Vpin (V)1.0571.2151.4081.6461.863
NFWC (e–)30944335551667257966
W (μm)2.8422.7922.8452.8452.845





Table1.
Vpin, NFWC and depletion depth (W) with different d.



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d (μm)0.60.70.80.91.0
Vpin (V)1.0571.2151.4081.6461.863
NFWC (e–)30944335551667257966
W (μm)2.8422.7922.8452.8452.845








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Figure6.
(Color online) Potential and depletion region distribution with different single-finger PPD widths.




Table 1 shows that the NFWC and Vpin of the PPD will increase as the width of finger-shaped PPD increases. Nevertheless, the design of d is not the larger the better. Because, the depletion width of PPD is:









$${W_{
m{dep}}} = sqrt {frac{{2{varepsilon _{
m{r}}}{varepsilon _0}left( {{N_{
m{A}}}{
m{ + }}{N_{
m{D}}}}
ight)left( {{V_{
m{b}}} - {V_{
m{s}}}}
ight)}}{{q{N_{
m{A}}}{N_{
m{D}}}}}},$$

(4)



where εr and ε0 are the relative dielectric constant of silicon and vacuum dielectric constant, NA is the doping concentration of the P-type region, Vb is the built-in potential in the PPD equilibrium state, and VS is the external voltage. This formula shows that the depletion region width of PPD is mainly related to the doping concentration of PPD and the applied bias voltage. Therefore, increasing d without changing VS, NA, and ND will affect the depletion state of PPD. When d > Wdep, PPD will not be fully depleted, resulting in image lag. Thus, the design value of d must be selected in a compromise. Fig. 6(f) shows the potential distribution of PPD under different d. The simulation results indicate that the potential barrier and potential well on the PPD charge transfer path are relatively small when d is 0.8 μm (within the range where the electron thermal motion can pass). Therefore, 0.8 μm is the optimal choice for the finger-shaped PPD width.



Fig. 7 shows the change in the number of electrons in the PPD (in Fig. 6(c)) over time. As can be seen from the figure, the number of electrons in PPD when saturated is:






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Figure7.
(Color online) The number of electrons in PPD based on TCAD 2D simulation.










$$begin{array}{l} {N_{{
m{PPD}}}} = {
m{eDensity}}left( {mu {{
m{m}}^2}/{
m{c}}{{
m{m}}^3}}
ight) times {{W}};(mu {
m{m}}) times {10^{-12}} quad quad {
m{ = 6}}{
m{.3857}} times {10^{15}} times 1 times {10^{-12}} approx 6385, end{array} $$

(5)



where eDensity is the number of electrons in the PPD obtained by TCAD 2D simulation, and W is the width of the PPD. Similarly, the number of electrons in the PPD after the charge transfer can be calculated to be zero. Therefore, the charge transfer efficiency of PPD is [(6385 – 0) / 6385] × 100% = 100%.




3.3
The simulation design of PPD finger spacing




Similar to the design of the finger-shaped PPD width, the design of the PPD spacing also needs to be compromised. Based on the PPD width of 0.8 μm and the step size of 0.1 μm, the simulation results were obtained when the PPD spacing is 0.9–1.4 μm. Fig. 8 shows the depletion region zone and potential distribution after charge transfer at different spacings.






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Figure8.
(Color online) Depletion zone and potential distribution with different PPD spacing.




The simulation diagrams indicate that the smaller the PPD spacing, the more complete the depletion zone of the adjacent single-finger PPD. However, if the spacing is too small, then the overall doping concentration of the PPD will be higher, which will cause the Vpin to be higher. When Vpin ≥ Vresert – Vdrop, it will seriously affect the signal charge transfer speed, and even lead to partial depletion of PPD. Vresert is the reset level of the FD, Vdrop is the voltage drop of the FD after the signal charge is completely transferred from the PPD to the FD. Table 2 extracts the Vpin results under the above-mentioned different PPD spacing. When the spacing is less than 1.1 μm, Vpin will increase significantly. The PPD will not be fully depleted when it is smaller than 0.9 μm, which is consistent with the above analysis. Hence, it is necessary to compromise to select the size of the PPD when designing the PPD, that is, to ensure that the PPD spacing is about 1.1 μm.






Spacing (μm)1.41.31.21.11.00.9
Vpin (V)1.3821.4151.4241.4381.506Not fully depleted





Table2.
Vpin with different PPD spacing.



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Spacing (μm)1.41.31.21.11.00.9
Vpin (V)1.3821.4151.4241.4381.506Not fully depleted





Figs. 9(a) and 9(b) show the changes in the number of electrons in the PPD over time before and after pixel optimization, respectively. These two pictures were obtained under the same simulation conditions. From Fig. 9(a), the number of electrons before and after charge transfer in PPD is 60912 and 14427, respectively. In other words, the charge transfer efficiency of the cubic PPD is 76.315%. From Fig. 9(b), the number of electrons before and after charge transfer in PPD is 15901 and 0, respectively. Hence, the proposed pixel structure can achieve a good charge transfer efficiency, that is, a charge transfer efficiency of 100%.






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Figure9.
(Color online) The number of electrons in PPD based on TCAD 2D simulation. (a) Using the process conditions of Fig. 2. (b) Using the process conditions of Fig. 8(d).





3.4
Further optimization of FWC




To further improve the pixel full well capacity, this paper proposes a PPD structure as shown in Fig. 10. Fig. 10(b) is a sectional structural view of the PPD taken along the AA' direction in Fig. 10(a). Fig. 10(c) is a TCAD device simulation diagram corresponding to Fig. 10(b). Except that the implantation zone of the first N-type ion implantation N1 is extended to the right, the remaining process conditions are the same as the foregoing. Compared with before the improvement, this structure not only increased the capacitance value of the PPD, but also collected photons incident at a certain angle into the PPD, thereby greatly improving the full well capacity of the pixel.






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Figure10.
(Color online) The special finger-shaped PPD structure proposed in this paper: (a) three-dimensional structure, (b) sectional structural view, (c) 2D device simulation diagram.





4.
Measurement results and analysis




In this paper, a front-illuminated CIS made in 0.18 μm CMOS process is designed and measured. The pixel design of this CIS uses the process parameters obtained through the TCAD device simulation described above. Based on the limitation of the pixel size and the area consumption of other transistors in the pixel, the final designed photodiode area is 4.6 × 4.6 μm2, the gate length of the transfer transistor is 0.6 μm, the single-finger PPD width is 0.8 μm and the spacing is 1.1 μm. To further improve the signal-to-noise ratio of CIS, binning technology is used in this paper to realize the accumulation of the output signals of two pixels. At the same time, so as to ensure the uniformity of the pixel array in the CIS, a 2 × 2 pixel unit is finally designed as shown in Fig. 11(a). As shown in Fig. 11(b), the structure diagram of PPD, transmission gate (TG), and FD in one pixel is shown.






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Figure11.
(Color online) Pixel layout and the main layout level of PPD-TG-FD. (a) 2 × 2 pixel unit. (b) Layout of PPD-TG-FD.




With a gain of 1.125 times and an exposure time of 124.6 ms, the output of the test chip under uniform illumination with different irradiances was measured in this paper. The measurement data was processed and analyzed with MATLAB and photon transfer theory. The photoresponse and FWC of pixels with different PPD spacings were obtained, as shown in Figs. 12 and 13, respectively. Fig. 12 shows the output of the test chip, the dimension of the output is ADU. The relationship of ‘ADU’ equivalent to ‘e?’ is:






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Figure12.
Photoresponse with different single-finger spacing.






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Figure13.
(Color online) FWC with different spacing (Before widening N1).










$${
m{FWC}}left( {{{
m{e}}^ - }}
ight) = frac{{{
m{FWC}}left(
m{ADU}
ight)}}{{Kleft( {
m{ADU}/{{
m{e}}^ - }}
ight)}},$$

(6)



where K represents the system gain of the image sensor, FWC (ADU) and FWC (e?) are the test chip output when the pixel is saturated. K is also expressed as the slope of the linear region of the photon transmission curve (PTC) during the rising phase. The measurement results are consistent with the simulation results in Table 2, that is, the number of signal charges (full well capacity) collected when the PPD is saturated will decrease with the increase of spacing. When the spacing is closest to 1.1 μm, it has the best FWC performance.



Based on these measurement conditions, the photoresponse and PTC of the special finger-shaped PPD structure (shown in Fig. 10(a)) is shown in Figs. 14(a) and 14(b), respectively. From the photoresponse, the FWC (ADU) is 11772 ADU. And, by linear fitting of the PTC curve, K is calculated to be 0.17148 ADU/e–. Therefore, FWC (e–) is also 68650e– according to Eq. (6), which is an increase of 8845e– compared to the FWC (59805e–) before the further improvement. Therefore, the proposed PPD structure can effectively improve the full well capacity of a pixel.






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Figure14.
(Color online) The measurement results of test chip: (a) photoresponse of the pixel using the proposed PPD structure, (b) PTC of the pixel using the proposed PPD structure.




Table 3 summarizes the FWC performance comparison with other imaging devices in Refs. [20–23]. It shows that the PPD structure proposed in this paper effectively improves the full well capacity of CIS.






ParameterThis workRef. [20]Ref. [21]Ref. [22]Ref. [23]
Technology0.18 μm CMOS90 nm CMOS0.13 μm CMOS0.18 μm CMOS0.18 μm CMOS
Pixel size (μm2)6.00 × 6.005.86 × 5.865.60 × 5.605.60 × 5.606.50 × 6.50
FWC (e-)686503045023000474506400





Table3.
Performance comparison between the pixel test results with a PPD of finger shape and related literature.



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ParameterThis workRef. [20]Ref. [21]Ref. [22]Ref. [23]
Technology0.18 μm CMOS90 nm CMOS0.13 μm CMOS0.18 μm CMOS0.18 μm CMOS
Pixel size (μm2)6.00 × 6.005.86 × 5.865.60 × 5.605.60 × 5.606.50 × 6.50
FWC (e-)686503045023000474506400






5.
Conclusion




This paper designs a CMOS image sensor with high full-well capacity based on 0.18 μm CMOS process. The finger-shaped PPD structure and the additional N-type ion implantation are used to increase the contact area of the PN junction and the unit-area capacitance of the PPD region, thereby improving the full well capacity of the CIS. Through simulation analysis, the pixel with this structure and process conditions has a depletion region depth of 2.8 μm and a charge transfer efficiency of 100%. The measurement results show that the full well capacity can reach 68650e–. Compared with the conventional structure, the proposed PPD structure can effectively improve the full well capacity of the pixel.




Acknowledgments




This work was supported by the Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology.



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