A 5 Gb/s CMOS adaptive equalizer for serial link

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本站小编 Free考研考试/2022-01-01

1.
Introduction

In wire-line systems, where the channel can roughly be modeled as a low-pass filter, intersymbol interference (ISI) would be introduced when the data rate is much higher than the bandwidth of the channel^[1]. As bit rates increase in computer systems, the frequency-dependent losses have become a critical issue, and the serious attenuation of amplitude versus frequency can make the eye diagram of the received data stream deteriorate. Once the eye diagram is too narrow or totally closed, the data cannot be detected correctly by the next device. A straightforward solution for re-shaping the eye is to design an adaptive equalizer^[1–16] in the receiver with automatic tuning capability; by this method it would not result in an under- or over-compensation for the attenuation of high-frequency components. Linear analog equalizer^{[1, 7–12]}, which can provide good ISI and jitter cancellation with acceptable power dissipation and integration complexity, has been developed widely in multi-Gb/s applications.

In this paper, a new adaptation scheme is implemented based on the continuous-time linear equalizer (CTLE) tuning algorithm in Ref. [7]. With a power consumption of 81.7 mW in the power supply of 1.8 V, the design can compensate for a cable loss up to 15 dB at 2.5 GHz.

This work starts with a brief introduction of the equalizer architecture proposed, following with the detailed analysis of each block, including equalizer amplifier, limiter amplifier, variable gain amplifier (VGA), and the adaptation algorithm. In the third part, experiment results and performance comparison are provided and the paper ends with conclusions.

2.
Implementation of adaptive equalizer

The block diagram of the presented equalizer architecture is shown in Fig. 1. The signal path consists of equalizer amplifier (EA), limiter amplifier (LA), transmitter buffer, and the adaptation loop including variable gain amplifier, low-pass filters (LPF), high-pass filters (HPF), power detector and the digital control FSM (finite state machines) block. A synchronized sampler is implemented to sample the comparison result of high-frequency energy between the EA output and VGA output through the error amplifier integrated in the equalizer loop, and collaborate with the FSM to control the adaptation flow. In the equalizer system, the EA block is used for boosting the high frequency components of interest, which is obtained by placing a low-frequency zero before the main pole. Limiter amplifier can amplify the signal fed by EA and limit its output amplitude to 1050 mV. Transmitter driver is designed to drive the signal out to the chip with the necessary driving capability.

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Figure1.
The proposed equalizer architecture.

As seen from Fig. 1, the adaptation function can be achieved through two loops: the low-frequency gain loop and the equalizer loop. The low-frequency gain loop is implemented by the low-pass filter, power detection and error amplifier. By comparing the low frequency energy between the VGA's output and EA's output after the low-frequency filter, a resulting error signal is generated and feedback to adjust the gain of the VGA. The equalizer loop consists of the high-pass filter, power detection, error amplifier and digital control FSM block, where the high frequency energy of the EA output and VGA output are compared by power detector and the resulting signal is used to optimize the equalizer level controlled by FSM. During equalizer loop training, the equalization level eq<3:0> will increase by 1.5 dB step until the state of error amplifier change, meaning that an appropriate equalization level is achieved.

2.1
Equalizer amplifier

The equalizer amplifier operates as a high-pass filter with parallel R–C network as the source degeneration, as shown in Fig. 2. The transfer function is as follows:

$$frac{{{V_{
m {out}}}}}{{{V_{
m {in}}}}} = frac{{{g_{
m m}}{R_{
m L}}}}{{1 + {g_{
m m}}frac{{{R_{
m s}}}}{2}}} frac{{1 + {R_{
m s}}{C_{
m S}} { s}}}{{left(1 +displaystyle frac{{{R_{
m s}}{C_{
m S}} s}}{{1 + {g_{
m m}}frac{{{R_{
m s}}}}{2}}}
ight) (1 + {R_{
m L}}{C_{
m L}} s)}}.$$

(1)

Based on Eq. (1), the circuit provides a zero of ${w_{
m z}} = 1/{R_{
m s}}{C_{
m s}}$

, the first pole of ${w_{
m p}} = (1 + {g_{
m m}}{R_{
m s}}/2){w_{
m z}}$

and the second pole of ${w_{
m p2}} = 1/{R_{
m L}}{C_{
m L}}$

. The second pole is the output pole, and it should be high enough not to interface with the high frequency peaking. According to Eq. (1), the suitable amount of the high frequency peaking can be achieved by adjusting the source degeneration load network, shown in Figs. 2(b) and 2(c) is the simulated frequency compensation response of the equalizer amplifier. Also, two stages of the equalizer cell are cascaded for achieving a total boost gain of 15 dB at the frequency of 2.5 GHz in this equalizer design.

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Figure2.
Equalizer amplifier cell with capacitive peaking. (a) Equalizer structure. (b) Source degeneration network. (c) Frequency response of the equalizer amplifier.

2.2
Limiting amplifier design

In the equalizer system, the transmitter driver works at current mode logic (CML), which requires a high slew rate for the output of limiter amplifier, as well as the minimum signal swing. This is why there is limiting amplifier as an interface between EA and transmitter driver. Furthermore, the LA works as the reference for both the two adaptation loops. Fig. 3 shows the diagram of the LA^[11] used in this design which is composed of a cascade of gain stages (A1–A4) and offset cancellation loop. Since the LA works in DC coupled mode, the offset cancellation should be implemented to prevent the shift of DC voltage in the output of LA. It should be noted that the high-pass cutoff frequency of the offset cancellation loop should be low enough, so as to minimize the voltage droop effect during long runs of 1 or 0 s. Assuming the auxiliary amplifier of the offset cancellation loop to be a single-pole system, then the small signal flow diagram of the LA can be simplified in Fig. 3(c), hence the transfer function of the LA is as follows:

$$frac{{{V_{
m {out}}}}}{{{V_{
m {in}}}}} = frac{{{A_{
m L}} [(1 + {R_1}{C_1}s - {R_1}{C_{
m m}}s) (1 + {R_2}{C_{
m m}}s + {R_2}{C_2}s) + {R_1}{R_2}{C_{
m m}}s({C_{
m m}}s - {g_{
m m1}})]}}{{(1 + {R_1}{C_1}s - {R_1}{C_{
m m}}s) (1 + {R_2}{C_{
m m}}s + {R_2}{C_2}s) + {R_1}{R_2}{C_{
m m}}s({C_{
m m}}s - {g_{
m m1}}) + {A_{
m L}}{R_{
m {in}}}{g_{
m m2}}{R_2}({g_{
m m1}} - {C_{
m m}}s)}},$$

(2)

where A_L is the gain of the limiter amplifier, both R₂ and C₂ are the load impedance of Aaux amplifier. If the condition of ${C_2} ll {C_1} = {C_{
m m}}$

holds, Eq. (2) can be simplified as

$$frac{{{V_{
m {out}}}}}{{{V_{
m {in}}}}} = frac{{{A_{
m L}} (1 + {R_2}{C_{
m m}}s - {g_{
m m1}}{R_1}{R_2}{C_{
m m}}s + {R_1}{R_2}C_{
m m}^2{s^2})}}{{(1 + {g_{
m m1}}{A_{
m L}}{R_{
m {in}}}{g_{
m m2}}{R_2}) + {R_2}{C_{
m m}}s(1 - {g_{
m m1}}{R_1} - {g_{
m m2}}{R_{
m in}}{A_{
m L}}) + {R_1}{R_2}C_{
m m}^2{s^2}}},$$

(3)

Eq. (3) appears rather complicated, an intuitive expression can be yielded by writing the numerator and denominator of Eq. (3) as Eq. (4) if assuming $|{w_1}| ll |{w_2}|$

$$D = left( {1 + frac{s}{{{w_1}}}}
ight)left( {1 + frac{s}{{{w_2}}}}
ight).$$

(4)

Then the intuitive transfer function of the LA can be expressed as follows:

$$frac{{{V_{{
m{out}}}}}}{{{V_{{
m{in}}}}}} approx frac{{{A_{
m{L}}}}}{{1 + {g_{{
m{m1}}}}{R_{{
m{in}}}}{g_{{
m{m2}}}}{R_2}{A_{
m{L}}}}}frac{{(1 + {g_{{
m{m1}}}}{R_1}{R_2}{C_{
m{m}}}s)left( {1 + frac{{{C_{
m{m}}}}}{{{g_{{
m{m1}}}}}}s}
ight)}}{{left( {1 + displaystylefrac{{{g_{{
m{m1}}}}{R_1} + {A_{
m{L}}}{g_{{
m{m2}}}}{R_{{
m{in}}}}}}{{{A_{
m{L}}}{g_{{
m{m2}}}}{R_{{
m{in}}}}{g_{{
m{m1}}}}}}{C_{
m{m}}}s}
ight)left( {1 + frac{{{R_1}{C_{
m{m}}}}}{{{g_{{
m{m1}}}}{R_1} + {A_{
m{L}}}{g_{{
m{m2}}}}{R_{{
m{in}}}}}}s}
ight)}}.$$

(5)

To achieve high bandwidth, EA’s load R_in is relatively small in the design. Hence the condition of ${g_{
m m1}}{R_1}gg $

$ {A_{
m L}}{g_{
m m2}}{R_{
m {in}}}$

holds, then Eq. (5) can be approximately given by

(6)

According to transfer function of Eq. (6), the design can prevent the shift of DC voltage in the output of LA, while the high-frequency signal will not be affected. In our design, the high-pass cutoff frequency is about 20 kHz in typical condition.

For the each gain stage implementation^[12] of the LA, as shown in Fig. 3(b), an active inductor load with NMOS is employed to extend the bandwidth. The gate of the active inductor is biased one NMOS threshold voltage above the power supply, generated by a charge pump. Hence the output swing of LA can be improved. For the reason that the input signal amplitude of LA has a wide range of value in terms of the cable lengths and material, a minimum gain of 17 dB is implemented in the design.

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Figure3.
(Color online) CMOS limiter amplifier with offset cancellation. (a) The structure of LA. (b) The gain cell of LA. (c) The small signal flow diagram.

2.3
VGA design

Fig. 4 shows the diagram of VGA, which is realized by using the source degeneration structure. The circuit provides the same transfer function as the EA block. As shown in Fig. 4, to adjust the gain of VGA, R_s in parallel with R_on of M1 are used as the source degeneration resistor, and V_g is produced by the adaptation loop shown in Fig. 1. By comparing the low-frequency energy of VGA’s output and EA’s output, the corresponding V_g can be obtained through the low-frequency gain loop, which is an analog negative feedback loop. The capacitor C_S is included in parallel with source degeneration resistor so as to enlarge the bandwidth.

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Figure4.
Structure of the source degeneration VGA.

2.4
Adaptation algorithm

The adaptation loop is used to adjust the equalization level automatically for compensating the loss of high frequency components. As shown in Fig. 1, the algorithm implemented by two loops: the low-frequency gain loop and the equalizer loop, where the VGA’s gain is trained by the low-frequency gain loop and the equalizer amplifier’s peaking gain is trained by the equalizer loop. In the system level, it is required that either the low-frequency gain loop completes training before the equalizer loop starts, or that both the loops work concurrently but with a much higher bandwidth of the low-frequency gain loop than that of the equalizer loop. There should be some tradeoff between the two methods on training time and power dissipation, the former method requires longer training time, while the latter method requires more power. In this work the former method has been implemented in the algorithm to save the power dissipation.

Fig. 5 illustrates how this adaptation algorithm works. After power up and high-speed signal is input to the chip, the low-frequency gain loop training starts. In this stage the output swings of the EA and VGA are compared by low-pass filter and power detector, and the resulting error is used to adjust the VGA’s gain. This loop is a negative feedback loop and the gain of VGA is continuous. This training has a time out clock of N₁ cycles, the appropriate gain of the VGA could be obtained during this training time. After the low-frequency gain loop training finish, the output swing of EA and VGA should be the same, and the FSM will begin the process of the equalizer loop training. In the equalizer training stage, the energy of high-frequency components of VGA output and EA output are compared by high-pass filter and power detector, and the resulting error is fed to the FSM which will adjust the equalization level according to the input. Once the system enters into the equalizer loop training, the equalization level of eq<3:0> starts with no equalizer and increases by 1.5 dB step, which is controlled by FSM block. The appropriate equalization level will be achieved through detecting err_amp_eq, the output of the error amplifier. The moment the signal goes from low to high, the appropriate equalization level is achieved and the adaptation is finished. The equalizer loop training also has a time out clock of (N₂–N₁) cycles in case the training cannot converge. When the training is completed, both adaptation loops are shut down to save power. The adaptation algorithm is clocked by an integrated 500 kHz oscillator, and the overall adaptation takes less than 190 μs to complete the training.

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Figure5.
(Color online) Operation of the adaptation algorithm.

For the design of HPF and LPF, the same structure is adopted as many other works, and the power detector used here is similar to another published work⁽¹⁾, the only change is that a linear amplifier is integrated in the design to cover the case when the input signal amplitude is very small.

2.5
Simulation results

In order to verify the adaptive equalizer, transient simulation with FR4 channel model were performed by using a random data stream at 5 Gbps and 1000 mV differential amplitude. As shown in Fig. 6 (a), the attenuation of the transmission channel model is ?7 dB at 2.5 GHz, Figs. 6(b) and 6(c) show the differential eye diagram of the output of the transmission channel and the output of the adaptive equalizer, respectively. The output eye of the transmission channel is almost close while the output eye of the system has an eye height of 1000 mV and a peak-to-peak jitter of 14 ps, as shown in Fig. 6(c). The jitter performance has been improved significantly by the adaptive equalizer.

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Figure6.
(Color online) Simulation results of overall topology. (a) Channel characteristic of S parameter. (b) Before equalization. (c) After equalization.

3.
Experiment results

The proposed circuit shown in Fig. 1 has been implemented in 0.13 μm CMOS technology. The equalizer is inductorless and has the advantages of low power consumption of 81.7 mW in a power supply of 1.8 V. As shown in Fig. 7, the signal path core occupies 0.3567 mm² (870 × 410 μm²).

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Figure7.
(Color online) Chip microphotograph.

Measurements were performed on the system with a designed 24-in PCB trace. The channel’s S-parameter is shown in Fig. 8(a), Figs. 8(b) and 8(c) show the input and output eye diagram measured at the equalizer, respectively. During the test, a signal of 5 Gbps pseudo random binary sequences (PRBSes) of 2²³?1 with BER = 10^?12 and 1000 mV peak-to-peak voltage is sent to the chip as the input data through the design PCB trace, and the output signal measured with an AC couple capacitor of 100 nF in series with 50 Ω resistor. As shown in Figs. 8(b) and 8(c), the input eye is almost closed after the transmission through the lossy PCB trace. After the equalization, the vertical eye opening is improved significantly, and the residual jitter at the output of the equalizer is 46 ps (0.23 UI). The eye diagram of the transmitted data is re-shaped by the designed circuit.

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Figure8.
(Color online) The experiment results. (a) Measurement of the S parameter of the channel. (b) Before equalization. (c) After equalization.

In Table 1 the characteristics of the proposed circuit are summarized and compared with the published paper in Refs. [7–9]. As shown in the table, higher data rate is achieved in the Ref. [7], which benefits from integrating inductor in the chip. The Ref. [9] consumes less power because of single stage equalizer amplifier and no limiting amplifier adopted in their architecture, resulting in lower gain in the low frequency. Compared with the Ref. [8], this work achieves better jitter performance while burning a comparable power.

Parameter	Ref. [7]	Ref. [9]	Ref. [8]	This work
Process (μm)	0.13	0.18	0.13	0.13
Data rate (Gb/s)	10	5.0	5.0	5.0
Equalizer boosting gain (dB)	0–20	4–16	0–12	0–15
Inductor	Yes	No	No	No
Output jitter (UI)	⁽¹⁾	0.28⁽²⁾	0.36⁽³⁾	0.23⁽⁴⁾
Supply voltage (V)	1.2	1.6	1.2	1.8
Power (mW)	25^**	48	34^**	81.7
Power (mW)	25^**	17.6^**	34^**	45.7^**
Area (mm²)	0.16	0.54^*	0.24	0.3567^*
Area include pad. *Exclude the output buffer. Notes: (1) Measured with 30-in FR4 board, no given quantized total Jitter. (2) Measured with 1.1-meter channel length. (3) Measured with 20-in + 8-in PCB trace. (4) Measured with 24-in PCB trace.

Table1.
Performance comparison of adaptive equalizer.

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Parameter	Ref. [7]	Ref. [9]	Ref. [8]	This work
Process (μm)	0.13	0.18	0.13	0.13
Data rate (Gb/s)	10	5.0	5.0	5.0
Equalizer boosting gain (dB)	0–20	4–16	0–12	0–15
Inductor	Yes	No	No	No
Output jitter (UI)	⁽¹⁾	0.28⁽²⁾	0.36⁽³⁾	0.23⁽⁴⁾
Supply voltage (V)	1.2	1.6	1.2	1.8
Power (mW)	25^**	48	34^**	81.7
Power (mW)	25^**	17.6^**	34^**	45.7^**
Area (mm²)	0.16	0.54^*	0.24	0.3567^*
Area include pad. *Exclude the output buffer. Notes: (1) Measured with 30-in FR4 board, no given quantized total Jitter. (2) Measured with 1.1-meter channel length. (3) Measured with 20-in + 8-in PCB trace. (4) Measured with 24-in PCB trace.

4.
Conclusions

A CMOS adaptive equalizer is designed to compensate for the transmission channel loss in multi-Gb/s applications. By employing the low-frequency gain loop and the equalizer loop, together with an intelligent flow control FSM, the proposed adaptation scheme can automatically adjust the low-frequency gain of the VGA and the high-frequency boosting level of the equalizer amplifier, so that a minimized residual jitter can be achieved. An offset cancellation loop is used to alleviate the offset of the signal path. Measurements were performed with a designed PCB trace, and experiment results demonstrate the jitter performance is improved significantly by the implemented chip.