关键词: 铜柱凸点/
界面行为/
失效机理/
热电应力
English Abstract
Interfacial reaction and failure mechanism of Cu/Ni/SnAg1.8/Cu flip chip Cu pillar bump under thermoelectric stresses
Zhou Bin1,2,Huang Yun2,
En Yun-Fei2,
Fu Zhi-Wei1,
Chen Si2,
Yao Ruo-He1
1.School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China;
2.Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The 5th Electronics Research Institute of the Ministry of Industry and Information Technology, Guangzhou 510610, China
Fund Project:Project supported by the Chinese Advance Research Program of Science and Technology, China (Grant No. JAB1728050), the Natural Science Foundation of Guangdong Province, China (Grant Nos. 2016A030310361, 2015A030310331), the Science and Technology Research Project of Guangdong Province, China (Grant No. 2015B090912002), and the Foundation of Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China (Grant No. 614280601041705).Received Date:03 September 2017
Accepted Date:14 October 2017
Published Online:20 January 2019
Abstract:Micro-interconnection copper pillar bumps are being widely used in the packaging areas of memory chip and high performance computer due to their high density, good conductivity and low noise. Studying the interfacial behavior of copper pillar bump is of great significance for understanding its failure mechanism and microstructure evolution in order to improve the reliability of flip chip package. The thermoelectric stress test, in-situ monitor, infrared thermography test, and microstructure analysis method are employed to study the interfacial reaction, life distribution, failure mechanism and their effect factors of Cu/Ni/SnAg1.8/Cu flip chip copper pillar interconnects under 9 groups of thermoelectric stresses including 2104-3104 A/cm2 and 100-150℃. Under thermoelectric stresses, the interfacial reaction of Cu pillar can be divided into three stages:Cu6Sn5 growth and Sn solder exhaustion; the Cu6Sn5 phase transformation, exhaustion and the Cu3Sn phase growth; voids formation and crack propagation. The rate of Cu6Sn5 phase transforming into Cu3Sn phase is positively correlated with the current density. There are four kinds of failure modes including Cu pad consumption, solder complete consumption and transformation into Cu3Sn, Ni plating layer erosion and strip voids. An obvious polar effect is observed during the dissolution of Cu pads on the substrate side and the Ni layer on the Cu pillar side. When Cu pad is located at the cathode, the direction of electron flow is the same as that of the heat flow, and it can accelerate the consumption of Cu pad and the growth of Cu3Sn. When Ni layer serves as the cathode, the electron flow can enhance the consumption of Ni layer. Under 150℃ and 2.5104 A/cm2, the local Ni barrier layer is eroded after 2.5 h, which results in the transformation of Cu pillar on the Ni side into (Cux, Niy)6Sn5 and Cu3Sn alloy. The life of Cu pillar interconnection complies well to the 2-parameter Weibull distribution with a shape parameter of 7.78, which is a typical characteristic of cumulative wear-out failure. The results show that the intermitallic growth behavior and failure mechanism at Cu pillar interconnects are significantly accelerated and changed under thermoelectric stresses compared with the scenario under the single high temperature stress.
Keywords: Cu pillar bump/
interfacial reaction/
failure mechanism/
thermoelectric stress
