黄正峰¹,
李先东¹,
陈鹏¹,
徐奇¹,
宋钛¹,
戚昊琛¹,
欧阳一鸣²,
倪天明^3,,
1.合肥工业大学电子科学与应用物理学院 合肥 230601
2.合肥工业大学计算机与信息学院 合肥 230601
3.安徽工程大学电气工程学院 芜湖 241000
基金项目:国家自然科学基金(61874156, 61874157, 61904001, 61904047)，安徽省自然科学基金(1908085QF272)

详细信息

作者简介:黄正峰：男，1978年生，教授，硕士生导师，研究方向是数字系统设计自动化
李先东：男，1996年生，硕士生，研究方向是集成电路软错误分析和系统可靠性设计
陈鹏：男，1995年生，硕士生，研究方向是硬件安全
徐奇：男，1991年生，讲师，研究方向是数字集成电路容错设计
宋钛：男，1982年生，博士生，研究方向是数字集成电路测试
戚昊琛：女，1981年生，高级实验师，研究方向是传感器与嵌入式系统
欧阳一鸣：男，1963年生，教授，研究方向是数字系统设计自动化等
倪天明：男，1991年出生，讲师，研究方向是三维集成电路容错设计

通讯作者:倪天明　timmyni126@126.com

中图分类号:TN43; TP302.8

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被引次数:0

出版历程

收稿日期:2020-05-05
修回日期:2021-05-15
网络出版日期:2021-08-11
刊出日期:2021-09-16

A Low-Cost Triple-Node-Upset-Resilient Latch Design

Zhengfeng HUANG¹,
Xiandong LI¹,
Peng CHEN¹,
Qi XU¹,
Tai Song¹,
Haochen QI¹,
Yiming OUYANG²,
Tianming NI^3,,
1. School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230601, China
2. School of Computer & Information, Hefei University of Technology, Hefei 230601, China
3. School of Electrical Engineering, Anhui Polytechnic University, Wuhu 241000, China
Funds:The National Natural Science Foundation of China (61874156, 61874157, 61904001, 61904047), Anhui Province Natural Science Foundation (1908085QF272)


摘要
摘要:随着集成电路特征尺寸的不断缩减，在恶劣辐射环境下，纳米级CMOS集成电路中单粒子三点翻转的几率日益增高，严重影响可靠性。为了实现单粒子三点翻转自恢复，该文提出一种低开销的三点翻转自恢复锁存器(LC-TNURL)。该锁存器由7个C单元和7个钟控C单元组成，具有对称的环状交叉互锁结构。利用C单元的阻塞特性和交叉互锁连接方式，任意3个内部节点发生翻转后，瞬态脉冲在锁存器内部传播，经过C单元多级阻塞后会逐级消失，确保LC-TNURL锁存器能够自行恢复到正确逻辑状态。详细的HSPICE仿真表明，与其他三点翻转加固锁存器(TNU-Latch, LCTNUT, TNUTL, TNURL)相比，LC-TNURL锁存器的功耗平均降低了31.9%，延迟平均降低了87.8%，功耗延迟积平均降低了92.3%，面积开销平均增加了15.4%。相对于参考文献中提出的锁存器，LC-TNURL锁存器的PVT波动敏感性最低，具有较高的可靠性。
关键词:锁存器/
抗辐射加固设计/
C单元/
自恢复/
三点翻转
Abstract:As the feature size of integrated circuits continues to scale down, under the harsh radiation environment, the probability of single event triple node upsets in nano-scale CMOS integrated circuits is increasing, seriously affecting reliability. In order to realize the resilient of single-event triple-node-upsets, a Low-Cost Triple-Node-Upset-Resilient Latch (LC-TNURL) is proposed. The latch is composed of seven C-elements and seven clock-gating C-elements, and has a symmetrical ring-shaped cross-interlock structure. Using the interceptive characteristics of the C-elements and the cross-interlock connection mode, after any three internal nodes are flipped, the transient pulse propagates inside the latch. After the C-elements is blocked in multiple stages, it will disappear step by step to ensure the LC-TNURL latch can self-recover to the correct logic state. Detailed HSPICE simulation shows that the power consumption of the LC-TNURL latch is reduced by an average of 31.9%, the delay is reduced by an average of 87.8%, the power-delay product is reduced by an average of 92.3% and the area overhead is increased by an average of 15.4% compared to other triple-node-upsets hardened latches (TNU-Latch, LCTNUT, TNUTL, TNURL). The LC-TNURL latch proposed in this paper is the least sensitive to PVT fluctuations and has high reliability compared with reference latches.
Key words:Latch/
Radiation hardening by design/
C-elements/
Resilient/
Triple node upsets



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