李斌康,,
田耕,
阮林波,
赵前,
吕宗璟
强脉冲辐射环境模拟与效应国家重点实验室 西安 710024
详细信息
作者简介:李海涛：男，1986年生，博士生，工程师，研究方向为快电子学
李斌康：男，1966年生，博士，研究员，研究方向为脉冲辐射探测、快脉冲电子学研究和系统研制
田耕：男，1978年生，博士，高级工程师，研究方向为仪器仪表控制、核电子学
阮林波：男，1973年生，硕士，高级工程师，研究方向为物理电子学
赵前：男，1994年生，硕士，研究实习员，研究方向为高速数字采集系统、数字信号处理
吕宗璟：男，1993年生，硕士，工程师，研究方向为模拟光纤传输、数字信号处理
通讯作者:李斌康 libk2008@sina.cn
中图分类号:TN79计量
文章访问数:362
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被引次数:0
出版历程
收稿日期:2020-09-07
修回日期:2021-02-25
网络出版日期:2021-03-30
刊出日期:2021-08-10
A General Method of Generating Code Density Calibration Signal for Time-to-Digital Converter and Its Realization
Haitao LI,Binkang LI,,
Geng TIAN,
Linbo RUAN,
Qian ZHAO,
Zongjing Lü
State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Xi’an 710024, China
摘要
摘要:该文提出一种通用的时间数字转换器(TDC)码密度校准信号产生方法，该方法基于相干采样理论，通过合理设置TDC主时钟和校准信号之间的频率差，结合输出信号保持电路，产生校准用的随机信号，在码密度校准过程中，随机信号均匀分布在TDC的延时路径上，实现对TDC的bin-by-bin校准。基于Xilinx公司的28 nm工艺的Kintex-7 现场可编程门阵列(FPGA)内部的进位链实现一种plain TDC，利用该方法校准plain TDC的码宽(抽头延迟时间)，研究校准了2抽头方式下的TDC的性能参数，时间分辨率(对应TDC的最低有效位，Least Significant Bit, LSB)为24.9 ps，微分非线性为(–0.84～3.1)LSB，积分非线性为(–5.0～2.2)LSB。文中所述的校准方法采用时钟逻辑资源实现，多次测试考核结果表明，单个延时单元的标准差优于0.5 ps。该校准方法采用时钟逻辑资源代替组合逻辑资源，重复性、稳定性较好，实现了对plain TDC的高精度自动校准。该方法同样适用于其他类型的TDC的码密度校准。
关键词:时间数字转换器/
码密度校准/
相干采样/
TDC主时钟/
校准信号
Abstract:This paper proposes a universal Time-to-Digital Converter (TDC) code density calibration signal generation method, which is based on the theory of coherent sampling. By reasonably setting the frequency difference between the TDC master clock and the calibration signal, combining with the output hold circuit, a random signal for calibration is generated to ensure that the random signal is evenly distributed on the TDC delay path to achieve Bin-by-bin calibration of TDC. The paper implements a carry chain plain TDC based on XILINX’s 28 nm Kintex-7 Field Programmable Gate Array (FPGA). The method is used to calibrate the code width (tap delay time) of plain TDC, and the performance parameters of TDC in 2-tap mode are studied and calibrated. The time resolution (corresponding to the least significant bit of TDC, Least Significant Bit, LSB) is 24.9 ps, with the differential nonlinearity is (–0.84～3.1) LSB, and the integral nonlinearity is (–5.0～2.2) LSB. The calibration method described in the paper is implemented using clock logic resources, and multiple tests show that the standard deviation of a single delay unit is better than 0.5 ps. This calibration method uses clock logic resources instead of combinatorial logic resources to realize high-precision automatic calibration of plain TDC, with good repeatability and stability. This method is also suitable for other types of TDC code density calibration.
Key words:Time-to-Digital Converter(TDC)/
Code density calibration/
Coherent sampling/
TDC master clock/
Calibration signal
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