孙晶茹^1,,,
李梦圆¹,
康可欣¹,
邾少鹏²,
SunYichuang³
1.湖南大学信息科学与工程学院 长沙 410082
2.北京邮电大学电子工程学院 北京 100089
3.英国赫特福德大学物理工程与计算机科学学院 哈特菲尔德 英国 AL10 9AB
基金项目:国家自然科学基金重大研究计划(91964108)，国家自然科学基金(61971185)，湖南省高校重点实验室开放基金(20K027)

详细信息

作者简介:孙晶茹：女，1977年生，副教授，研究方向为非线性电路与系统、图像加密
邾少鹏：男，1998年生，硕士生，研究方向为忆阻存储电路设计
SunYichuang：男，1960年生，教授，研究方向为无线和移动通信、射频和模拟电路、微电子设备和系统、机器学习和深度学习

通讯作者:孙晶茹　jt_sunjr@hnu.edu.cn

中图分类号:TN601; TN710

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出版历程

收稿日期:2020-12-31
修回日期:2021-04-05
网络出版日期:2021-04-19
刊出日期:2021-06-18

Design of Heterogeneous Memristor Based 1T2M Multi-value Memory Crossbar Array

Jingru SUN^1,,,
Mengyuan LI¹,
Kexin KANG¹,
Shaopeng ZHU²,
Yichuang SUN³
1. College of Computer Science and Electronic Engineering, Hunan University, Changsha 410082, China
2. School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100089, China
3. School of Physics, Engineering and Computer Science, University of Hertfordshire, Hatfield AL10 9AB, UK
Funds:The Major Research Project of the National Natural Science Foundation of China (91964108), The National Natural Science Foundation of China (61971185), The Open Fund Project of Key Laboratory in Hunan Universities (20K027)


摘要
摘要:忆阻器作为一种新型电子元件，具有尺寸小、读写速度快、非易失性和易于与CMOS电路兼容等特性，是实现非易失性存储器最具发展前景的技术之一。但是已有的多值存储交叉阵列存在电路结构复杂、漏电流和存储密度低等问题，影响了多值存储交叉阵列的实用性。该文提出一种基于异构忆阻器的多值存储交叉阵列，其中存储单元由1个MOS管和两个具有不同阈值电压和R_on阻值的异构忆阻器构成(1T2M)，可实现单个电压信号完成4值读写的操作，减少电流通路的同时简化了电路结构。通过PSpice进行仿真验证，表明所提出的1T2M多值存储器交叉阵列与已有工作相比，电路结构更简单，读写速度更快，并较好地克服了漏电流问题。
关键词:忆阻器/
存储器/
交叉阵列/
漏电流
Abstract:As a new type of electronic component, memristor has the characteristics of small size, fast reading and writing speed, non-volatile and easy to be compatible with CMOS circuits. It is one of the most promising technologies to realize non-volatile memory. However, the existing multi-value storage cross array has problems such as complex circuit structure, sneak path problem and low storage density, which affect the practicability of the multi-value storage cross array. In this paper, a multi-value memory crossbar array based on heterogeneous memristors is proposed, in which the memory cell is composed of one Transistor and two heterogeneous Memristors (1T2M) with different threshold voltages and R_on resistance values. A single voltage signal completes the four-value read and write operation, which reduces the current path and simplifies the circuit structure. Simulation verification by PSpice shows that compared with existing work, the proposed 1T2M multi-value memory crossbar array has simpler circuit structure, higher storage density, faster reading and writing speed, and overcomes better the leakage current problem.
Key words:Memristor/
Memory/
Crossbar array/
Sneak paths



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