别梦妮1,
陈韬1,
吴艾青1,
南龙梅2
1.解放军信息工程大学 郑州 450000
2.复旦大学专用集成电路与系统国家重点实验室 上海 200433
详细信息
作者简介:李伟：男，1983年生，副教授，博士生导师，研究方向为密码处理器设计、ASIC专用芯片设计
别梦妮：女，1997年生，硕士生，研究方向为智能化可重构芯片电路与架构
陈韬：男，1979年生，副教授，硕士生导师，研究方向为安全专用芯片设计
吴艾青：男，1997年生，硕士生，研究方向为智能化可重构芯片电路与架构
南龙梅：女，1981年生，博士生，研究方向为大规模集成电路设计、专用集成电路设计
通讯作者:李伟 liwei12@fudan.edu.cn
中图分类号:TN918.4; TP316.4计量
文章访问数:262
HTML全文浏览量:64
PDF下载量:38
被引次数:0
出版历程
收稿日期:2021-01-04
修回日期:2021-04-07
网络出版日期:2021-04-16
刊出日期:2021-06-18
Research on Energy Efficiency Probability Model and Architecture of RISCV Cryptographic Processor
Wei LI1,,,Mengni BIE1,
Tao CHEN1,
Aiqing WU1,
Longmei NAN2
1. PLA Information Engineering University, Zhengzhou 450000, China
2. State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China
摘要
摘要:该文以高能效为目标，建立了密码专用处理器能效概率模型，并指导高能效密码专用处理器体系结构设计。该文将面向密码领域的专用指令处理器设计空间探索问题描述为“1”值在配置矩阵中的定位问题，通过引入概率矩阵进一步将定位问题转化为最优配置的概率问题，并基于机器学习思想提出了密码专用处理器最高能效概率模型。实验证明，该文提出的能效概率模型平均经过2300次迭代输出最终结果，且预测准确率达到92.7%。根据最高能效概率模型，对密码专用处理器设计空间进行探索，获取满足高能效需求的密码专用处理器运算单元集合，以扩展指令的方式将其集成到开源通用64位RISCV处理器核心Araine中，提出高能效密码专用处理器体系结构。将该处理器在CMOS 55 nm工艺下进行逻辑综合，结果表明，该文提出的RISCV密码专用处理器与扩展前相比面积增大了426874 μm2，关键延迟增加了0.51 ns，完成密码算法总时间面积积增幅之和为0.46，执行常见密码算法能效比在1.61～35.16 Mbps/mW范围内。
关键词:密码处理器/
机器学习/
能效概率模型/
高能效
Abstract:This paper establishes an energy efficiency probability model for a dedicated cryptographic processor, and guides the design of the cryptographic processor. The design space exploration problem of a processor is designed as the positioning problem of "1" values ??in the configuration matrix. The probability matrix is introduced to transform the positioning problem into an optimal configuration probability problem. Based on the idea of machine learning, a probability model for the highest energy efficiency of a dedicated cryptographic processor is proposed. Experiments prove that the energy efficiency probability model in this paper outputs the final result after 2300 iterations on average, and the prediction accuracy rate reaches 92.7%. According to the highest energy efficiency probability model, a collection of computing units that meet high energy efficiency requirements can be obtained, and they are integrated into the open source general-purpose 64 bit RISCV processor core named Ariane. A dedicated processor for energy-efficient cryptography is built. The processor is synthesized under the CMOS 55 nm process, and the results show that compared with Ariane, the area of the proposed cryptographic processor increases by 426874 μm2, the key delay increases by 0.51 ns, and the sum of the increasing total time area of the cryptographic algorithm is 0.46, the energy efficiency ratio of common cryptographic algorithms is within the range of 1.6～35.16 Mbps/mW.
Key words:Cryptographic processor/
Machine learning/
Energy efficiency probability model/
High energy efficiency
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https://jeit.ac.cn/article/exportPdf?id=3f5d3698-0bdd-4507-9332-c90901f2d722
