陈治文,
汪鹏君,
宁波大学电路与系统研究所 ??宁波 ??315000
基金项目:国家自然科学基金(61474068, 61306041)，浙江省公益技术应用研究计划项目(2016C31078)，宁波大学研究生科研创新基金
详细信息
作者简介:张会红：女，1976年生，副教授，研究方向为集成电路设计与优化、控制理论与应用
陈治文：男，1993年生，硕士，研究方向为集成电路逻辑优化
汪鹏君：男，1966年生，教授，博士生导师，研究方向为低功耗、高信息密度集成电路和安全芯片设计及理论研究
通讯作者:汪鹏君 wangpengjun@nbu.edu.cn
中图分类号:TN79+1; TP391.7计量
文章访问数:1900
HTML全文浏览量:382
PDF下载量:40
被引次数:0
出版历程
收稿日期:2018-05-10
修回日期:2018-11-21
网络出版日期:2018-12-04
刊出日期:2019-03-01
Area and Delay Optimization of Binary Decision Diagrams Mapped Circuit
Huihong ZHANG,Zhiwen CHEN,
Pengjun WANG,
Institute of Circuits and Systems, Ningbo University, Ningbo 315000, China
Funds:The National Natural Science Foundation of China (61474068, 61306041), Zhejiang Province Public Welfare Technology Application Research Project (2016C31078), The Scientific Research Foundation of Graduate School of Ningbo University
摘要
摘要:二叉决策图(BDD)是一种数据结构，广泛应用于数字电路的逻辑综合、测试和验证等领域。将BDD每个结点映射成2选1数据选择器(MUX)可得到BDD映射电路。该文提出一种BDD映射电路的面积和延时优化方法。首先把待优化电路转换成BDD形式，然后逐一搜索BDD中存在的菱形结构，进而通过路径优化实现结点的删减和控制变量的更改，并将所得结果BDD映射成MUX电路，最后用多个MCNC基准电路进行测试，将该文方法与经典综合工具BDS, SIS等方法相比较，BDD总结点数比BDS减少了55.8%，映射电路的面积和延时比SIS分别减小了39.3%和44.4%。
关键词:电路优化/
二叉决策图/
数据选择器/
延时优化
Abstract:Binary Decision Diagrams (BDD) is a data structure that can be used to describe a digital circuit. By replacing each node in a BDD with a 2-to-1 Multiplexer (MUX), a BDD can be mapped to a digital circuit. An area and delay optimization method on BDD mapped circuit is presented. A traditional Boolean circuit is converted into BDD form, and then diamond structure constructed by nodes is searched in the BDD, corresponding nodes are deleted and control signals of the modified nodes are updated by paths optimization, finally, the result BDD is mapped to a MUX circuit. The proposed method is test by a number of Microelectronics Center of North Carolina (MCNC) Benchmarks. Compared with the classical synthesis tools Sequential Interactive System (SIS) and BDD-based logic optimization System (BDS), the average number of nodes by the proposed methods is 55.8% less than that of BDS, and average circuit’s area and delay are reduced by 39.3% and 44.4% than that of the SIS, respectively.
Key words:Circuit optimization/
Binary Decision Diagrams (BDD)/
Multiplexer/
Delay optimization
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