上海交通大学计算机科学与工程系导师教师师资介绍简介-Jingwenleng - 上海交通大学师资导师 - Free考研考试

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上海交通大学计算机科学与工程系导师教师师资介绍简介-Jingwenleng

本站小编 Free考研考试/2021-01-02

I am a tenure-track Associate Professor in John Hopcroft Computer Science Center and Computer Science and Engineering Department at Shanghai Jiao Tong University. I received the Ph.D. degree from the University of Texas at Austin. My past research focused on improving the efficiency and resiliency of general-purpose GPUs. I was the lead co-author for GPUWattch, one of the most widely used open-sourced GPU power model. My CV is available here.

I am currently interested at building intelligent and robust system for artificial intelligence. I believe the virtuous cycle of algorithm-software-hardware is the key to enable next-generation AI technology in practice. This is the golden age to conduct research on computer architecture and system. I am looking for self-motivated students who would like to conduct high-quality research in building efficient and reliable systems for deep learning. Please send me an email if you are interested at working with me.

Office: 闵行校区软件学院1号楼410
Lab (Mostly)：闵行校区电信群楼3号楼119
Email: leng-jw at sjtu dot edu dot cn

News

I am teaching EI 200 Computer Organization in the spring 2020. The course information can be found here.
Project "Robust and Efficient System Architecture for AI Applications with Effective Path" is funded by MSRA.
I am co-teaching graduate course Advanced Computer Architecture. The course information can be found here.
Project "Asymmetric Resilience for Reliable Accelerator-Rich Systems" is funded NSFC.
I am teaching EE 204 Embedded System Principle and Practice (嵌入式系统原理与实验) in the spring 2018. The course information can be found here.

I am looking for self-motivated graduate students as well as undergrads who are interested in conducting high-quality research in building efficient and reliable systems for deep learning.

Education
Ph.D., The University of Texas at Austin, 2012 - 2016
M.S., The University of Texas at Austin, 2010 - 2012
B.S., Shanghai Jiao Tong Univerisity, 2006 - 2010

Industry Experience
IBM T.J. Watson Research Center, Research Intern, March 2015 - December 2016
SRI International, Research Intern, Summer 2013
Samsung Austin Research and Development Center, Summer Intern, Summer 2011

Architecture for Deep Learning

[COLING’20]

How Far Does BERT Look At: Distance-based Clustering and Analysis of BERT’s Attention

[SC’20]

Accelerating Sparse DNN Models without Hardware-Support via Tile-Wise Sparsity

[MICRO’20]

Ptolemy: Architecture Support for Robust Deep Learning

[PACT’20]

Low-Latency Proactive Continuous Vision

[ICDCS’20]

CODA: Improving Resource Utilization by Slimming and Co-locating DNN and CPU Jobs

[DAC’20]

Balancing Efficiency and Flexibility for DNN Acceleration via Temporal GPU-Systolic Array Integration

[CAL’20]

Architectural Implication of Graph Neural Networks

[CVPR’19]

Adversarial Defense Through Network Profiling Based Path Extraction

[ICCD’19]

Ebird: Elastic Batch for Improving Responsiveness and Throughput of Deep Learning Services

[NPC’19]

Characterizing Perception Module Performance and Robustness in Production-Scale Autonomous Driving System

[CAL’19]

Asymmetric Resilience for Accelerator-Rich Systems

[CAL’19]

SVSoC: Speculative Vision Systems-on-a-Chip

Resiliency and Efficiency

[HPCA’20]

Asymmetric Resilience: A System Architecture for Transient Error Recovery in Accelerator-Rich Processors

[TDMR’20]

Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins

[JPDC’20]

Predicting and Reining in Application-level Slowdown on Spatial Multitasking GPUs

[TCAD’20]

Predictive Guardbanding: Program-driven Timing Margin Reduction for GPUs

[TCAD’20]

Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management

[IOLTS’19]

Modern Hardware Margins: CPUs, GPUs, FPGAs

[TC’19]

DR Refresh: Releasing DRAM Potential by Enabling Read Accesses under Refresh

[MICRO’18]

Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs

[ICCD’18]

DR DRAM: Accelerating Memory-Read-Intensive Applications

[DAC’18]

Efficient And Reliable Power Delivery In Voltage-stacked Manycore System With Hybrid Charge-recycling Regulators

[DAC’17]

IVORY: Early Stage Design Space Exploration Tool for Integrated Voltage Regulators

[MICRO’15]

Safe Limits on Voltage Reduction Efficiency in GPUs: a Direct Measurement Approach

[MICRO’15]

Adaptive Guardband Scheduling to Improve System-Level Efficiency of the POWER7+

[HPCA’15]

GPU Voltage Noise: Characterizing and Hierarchical Smoothing Spatial and Temporal Voltage Noise Interference in GPU Architectures

[ISLPED’14]

GPUVolt: Modeling And Characterizing Voltage Noise In GPUs

[MICRO’13]

A Locality-Aware Memory Hierarchy for Energy-Efficient GPU Architectures

[ISCA’13]

GPUWattch: Enabling Energy Optimization in GPGPUs

[CAL’12]

Exploiting Webpage Characteristics for Energy-Efficient Mobile Web Browsing

Cloud Computing

[IPDPS’20]

Sturgeon: Preference-aware Co-location for Improving Utilization of Power Constrained Computers

[IPDPS’19]

Themis: Predicting and Reining in Application-Level Slowdown on Spatial Multitasking GPUs

[ICS’19]

Avalon: Towards QoS Awareness and Improved Utilization through Multi-Resource Management in Datacenters

[TACO’18]

Bandwidth and Locality Aware Task-stealing for Manycore Architectures with Bandwidth-Asymmetric Memory

Misc.

[FCS’19]

Probabilistic Robust Regression With Adaptive Weights—a Case Study On Face Recognition

[WNTC’14]

Lightweight Detection and Recovery Mechanisms to Extend Algorithm Resiliency in Noisy Computation

[SELSE’14]

Energy Efficiency Benefits of Reducing the Voltage Guardband on the Kepler GPU Architecture

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