罗建禄 副教授
所在系所制造技术与装备自动化研究所
办公电话616304
通讯地址上海市闵行区东川路800号上海交通大学机械楼D楼
电子邮件kainlulow@sjtu.edu.cn
个人主页http://me.sjtu.edu.cn/teacher_directory1/luojianlu.html


教育背景 PhD in Electrical Engineering, National University of Singapore, 2015
Master in Electrical Engineering, Purdue University, 2007
Bachelor in Electrical Engineering, Purdue University, 2005

工作经历 2019-2020: Hybrid Integrated Flexible Electronic Systems (HiFES) Lab, NUS, Singapore, Research Fellow
?Worked on the defect modeling to shed light on the impact of the defects on the electrical response of advanced transistors,
?Developed an efficient methodology combining the TCAD defect modeling and Machine-Learning predictive model for the defect diagnosis in advanced semiconductor technology nodes.

2015-2019: Globalfoundries Singapore, Senior Engineer
?Worked with internal design enablement, process integration, unit process module, optical proximity correct (OPC), and tapeout team across the USA, Germany, and Singapore to define and develop device truth table, mask generation rules/algorithms required for DRC / LVS / reticle procurement by advanced technology.
?Developed a novel methodology that leverages the knowledge of device physics and processing to transform the mask generation rules checking on the GDSOUT into a systematic and automatic manner.
2007-2010: Legend Design Technology, Inc. , Santa Clara, CA USA, Research & Development Engineer
?Worked on device modeling for Spice circuit simulator, involving the implementations of different MOSFET models to the simulator.
?Incorporated TSMC Modeling Interface (TMI) to the Spice simulator and the implementation certified by TSMC TMI Tool Qualification Program.

研究方向 Design and development of advanced electronics within the theoretical framework based on design and technology co-optimization (DTCO)
- Material Modeling
- Device Modeling
- Circuit Modeling

代表性论文专著 Journal Publications:
X. Zhang, K.-T. Lam, K. L. Low*, Y.-C. Yeo, and G. Liang, “Nanoscale FETs Simulation Based on Full-Complex-Band Structure and Self-Consistently Solved Atomic Potential”, IEEE Transactions on Electron Devices, vol. 64, no. 1, 58, Jan. 2017.
K. L. Low*, Y.-C. Yeo, and G. Liang, “Ultimate Performance Projection of Ultrathin Body Transistor Based on Group IV, III-V, and 2-D-Materials,” IEEE Trans. Electron Devices, vol. 63, no. 2, 773, Feb. 2016.
Y. Guo, X. Zhang, K. L. Low*, K.-T. Lam, Y.-C. Yeo, and G. Liang, "Effect of Body Thickness on the Electrical Performance of Ballistic n-Channel GaSb Double gate Ultrathin-Body Transistor", IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 788 - 794, Mar. 2015.
Y. Tong, Q. Zhou, K. L. Low*, L. X. Wang, L. H. Chua, T. Thanigaivelan, T. Henry, and Y.-C. Yeo, "Cold silicon pre-amorphization implant and pre-silicide sulfur implant for advanced nickel silicide contacts," IEEE Transactions on Electron Devices, vol. 61, no. 10, pp. 3499-3506, Aug. 2014.
K. L. Low*, W. Huang, Y.-C. Yeo, and G. Liang, “Ballistic Transport Performance of Silicane and Germanane Transistors,” IEEE Trans. Electron Devices, vol. 61, no. 5, 1590, May 2014.
Y. Yang, G. Han, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low*, and Y.-C. Yeo, "Germanium-tin p-channel tunneling field-effect transistor: Device design and technology demonstration," IEEE Transactions on Electron Devices, vol. 60, no. 12, pp. 4048-4056, Nov. 2013.
Y. Yang, K. L. Low*, W. Wang, P. Guo, L. Wang, G. Han, and Y.-C. Yeo, "Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study," Journal of Applied Physics, vol. 113, no. 19, pp. 194507, May 2013.
K.-H. Goh, Y. Cheng, K. L. Low*, E. Y. J. Kong, C.-K. Chia, E.-H. Toh, and Y.-C. Yeo, "Physical model for gallium arsenide growth on germanium fins with different orientations formed on 10° offcut germanium-on-insulator substrate," Journal of Applied Physics, vol. 113, no. 4, pp. 044103, Jan. 2013.
K. L. Low*, C. Zhan, G. Han, Y. Yang, K.-H. Goh, P. Guo, E.-H. Toh, and Y.-C. Yeo, “Device physics and design of a L-shaped Germanium source tunneling transistor,” Japanese J. Applied Physics, vol. 51, no. 2, 02BC04, Feb. 2012.
K. L. Low*, Y. Yang, G. Han, W. Fan, and Y.-C. Yeo, "Electronic band structure and effective mass parameters of Ge1-xSnx alloys," J. Applied Physics, vol. 112, no. 11, 103715, Nov. 2012.
Y. Yang, P.-F. Guo, G.-Q. Han, K.-L. Low*, C.-L. Zhan, and Y.-C. Yeo, "Simulation study of tunneling field-effect transistor with extended source structures," Journal of Applied Physics, vol. 111, no. 11, pp. 114514, Jun. 2012.
Conferences：
C. W. Teo, K. L. Low*, V. Narang, and V. Thean, “TCAD-Enabled Machine Learning Defect Prediction to Accelerate Advanced Semiconductor Device Failure Analysis”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, Sep. 4 -6, 2019.
S. Luo, K. L. Low*, X. Zhang, Q. Zhao, H. Lin, and G. Liang, “A Computational Study of Fundamentals and Design Considerations for Vertical Tunneling Field-Effect Transistor”, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Feb. 28 – Mar. 2, 2017.
G. Liang and K. L. Low*, “A Computational Study of Tunneling Field-Effect Transistors: Challenges and Design Optimizations”, 230th Electrochemical Society Meeting, Honolulu, HI USA, Oct. 2 - 7, 2016.
S. Yadav, K.-H. Tan, Annie, K. H. Goh, S. Subramanian, K. L. Low*, N. Chen, B. Jia, S.-F. Yoon, G. Liang, X. Gong, and Y.-C. Yeo, “First Monolithic Integration of Ge P-FETs and InAs N-FETs on Silicon Substrate: Sub-120 nm III-V Buffer, Sub-5 nm Ultra-thin Body, Common Raised S/D, and Gate Stack Modules,” IEEE International Electron Device Meeting 2015 (IEDM), Washington, DC, USA, Dec. 7-9, 2015.
K. L. Low*, Y.-C Yeo, and G. Liang, “Voltage Scalability of Double-Gate Ultra-Thin-Body Field-Effect Transistors with Channel Materials from Group IV, III-V to 2D-Materials based on ITRS Metrics for Year 2018 and Beyond”, 72nd Device Research Conference, UC Santa Barbara, CA, Jun. 2014
Y.-C. Yeo, X. Gong, P. Guo, Y. Yang, L. Wang, Y. Tong, K. L. Low*, C. Zhan, R. Cheng, B. Liu, W. Wang, Q. Zhou, X. Xu, and Y. Dong, "Application of germanium-tin (GeSn) in field-effect transistors," IEEE Nanotechnology Materials and Devices Conference (NMDC), Taiwan, Taiwan, Oct. 6 - 9, 2013.
Y. Yang, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low*, G. Han, and Y.-C. Yeo, "Germanium-tin tunneling field-effect transistor: Device design and experimental realization," International Conference on Solid-State Devices and Materials (SSDM), Fukuoka, Japan, Sept. 24-27, 2013.
Y. Yang, S. Su, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low*, G. Zhang, C. Xue, B. Cheng, G. Han, and Y.-C. Yeo, "Towards direct band-to-band tunneling in p-channel tunneling field effect transistor (TFET): Technology enablement by germanium-tin (GeSn)," IEEE International Electron Device Meeting 2012 (IEDM), San Francisco, CA USA, Dec. 10-12, 2012.
K. L. Low*, Y. Yang, G. Han, W.-J. Fan, and Y.-C. Yeo, “Electronic band structure and effective masses of Ge1-xSnx alloys,” 222nd Electrochemical Society Meeting, Honolulu, HI USA, Oct. 7 - 12, 2012
Y. Yang, K. L. Low*, G. Han, and Y.-C. Yeo, "Germanium tin tunneling field effect transistor for sub-0.4 V operation," 222nd Electrochemical Society Meeting (ECS), Honolulu, HI USA, Oct. 7-12, 2012.
Y. Tong, S. Su, B. Liu, L. Wang, P. S. Y. Lim, W. Wang, K. L. Low*, G. Zhang, C. Xue, B. Cheng, G. Han, and Y.-C. Yeo, "Nickel stanogermanide ohmic contact on n-type germanium-tin (Ge1-xSnx) using Se and S implant and segregation," International Conference on Solid-State Devices and Materials (SSDM), Kyoto, Japan, Sept. 25-27, 2012.
K. H. Goh, Y. Cheng, K. L. Low*, E. Y. J. Kong, C.-K. Chia, E.-H. Toh, and Y.-C. Yeo, "Selective growth of gallium arsenide on germanium fins with different orientations formed on 10° offcut germanium-on-insulator substrate," International Conference on Solid-State Devices and Materials (SSDM), Kyoto, Japan, Sept. 25-27, 2012.
G. Han, Y. Yang, P. Guo, C. Zhan, K. L. Low*, K. H. Goh, B. Liu, E.-H. Toh, and Y.-C. Yeo, "PBTI characteristics of n-channel tunneling feld effect transistor with HfO2 gate dielectric: New insights and physical model," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 23-25, 2012.
K. L. Low*, C. Zhan, G. Han, Y. Yang, K. H. Goh, P. Guo, E.-H. Toh, and Y.-C. Yeo, “Tunnel field-effect transistor with L-shaped germanium source: Device physics and design,” Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials, Nagoya, Japan, Sep. 28 - 30, 2011, pp. 849 - 850