Design considerations of calibration DAC in self-calibrated SAR A/D converters
Publication in refereed journal


香港中文大学研究人员 ( 现职)

潘江鹏教授 (电子工程学系)

全文

数位物件识别号 (DOI) ○○@http://aims.cuhk.edu.hk/converis/portal/Publication/2$@○○

引用次数
Web of Sciencehttp://aims.cuhk.edu.hk/converis/portal/Publication/2WOS source URL
Scopushttp://aims.cuhk.edu.hk/converis/portal/Publication/2Scopus source URL

其它资讯

摘要A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results. ? http://aims.cuhk.edu.hk/converis/portal/Publication/2013 Elsevier Ltd.

着者Sun L., Pun K.-P.
期刊名称MICROELECTRONICS JOURNAL
出版年份http://aims.cuhk.edu.hk/converis/portal/Publication/2014
月份1
日期1
卷号45
期次1
出版社Elsevier BV
出版地Netherlands
页次14 - http://aims.cuhk.edu.hk/converis/portal/Publication/2http://aims.cuhk.edu.hk/converis/portal/Publication/2
国际标準期刊号00http://aims.cuhk.edu.hk/converis/portal/Publication/26-http://aims.cuhk.edu.hk/converis/portal/Publication/269http://aims.cuhk.edu.hk/converis/portal/Publication/2
语言英式英语

关键词ADC, Calibration DAC, Digital calibration, Successive approximation register ADC