Publication in refereed journal
香港中文大学研究人员 ( 现职)
| 潘江鹏教授 (电子工程学系) |
| 陈昌发教授 (电子工程学系) |
| 蔡潮盛教授 (电子工程学系) |
全文
| 数位物件识别号 (DOI) http://dx.doi.org/10.1109/TCSII.2004.824051 |
引用次数
Web of Sciencehttp://aims.cuhk.edu.hk/converis/portal/Publication/0WOS source URL
其它资讯
摘要In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.
着者Chan RPK, Choy OCS, Chan CF, Pun KP
期刊名称IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
出版年份2http://aims.cuhk.edu.hk/converis/portal/Publication/0http://aims.cuhk.edu.hk/converis/portal/Publication/04
月份5
日期1
卷号51
期次5
出版社IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
页次217 - 221
国际标準期刊号1http://aims.cuhk.edu.hk/converis/portal/Publication/057-713http://aims.cuhk.edu.hk/converis/portal/Publication/0
语言英式英语
关键词asynchronous circuit; D flip-flop; differential cascode voltage switch logic (DCVSL); latency; shift register
Web of Science 学科类别Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC
