Low Cost BIST Scheme Using LFSR-RC Reseeding

Bin Zhou¹, Mingxue Huo^1,2,Xinchun Wu³

(1. Research Center of Basic Space Science, Harbin Institute of Technology, Harbin 150001, China;2. Dept. of Microelectronics Science and Technology, Harbin Institute of Technology, Harbin 150001, China;3. School of Information Science and Technology, Southwest Jiaotong University, Chengdu 610031, China)



Abstract:

A novel BIST scheme for reducing the test storage (TS) is presented. The proposed approach relies on a two-dimensional compression scheme, which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters (RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the width of the test set, and conclude that the probability of encoding a n-ª«bitª« test cube with s specified bits using a (sª­ª«maxª«+1+20/n)-ª«stageª« LFSR with a fixed polynomial is 1-10-6. Experimental results for the ISCAS¡¯89 benchmark circuits show that compared with the previous schemes, the proposed scheme based on LFSR-RC reseeding requires 57£¥ less TS and 99.1£¥ test application time (TAT) with simple and uniform BIST control logic.

Key words:  built-in self-test  linear feedback shift register (LFSR)  ring counters(RCs)  test compression

DOI£º10.11916/j.issn.1005-9113.2015.03.008

Clc Number:TN47

Fund: