詹陈长副教授
个人简介
个人主页
詹陈长是南方科技大学深港微电子学院(国家示范性微电子学院)副教授。詹教授分别于2004、2007年获得上海复旦大学电子工程学士和微电子学与固体电子学硕士学位，于2011年获得香港科技大学电子及计算机工程博士学位。2006至2007年在上海芯原微电子有限公司担任实习模拟电路设计工程师，2011至2012年担任香港科技大学博士后研究员，2012至2014年在美国高通公司担任高级工程师, 专注于为下一代移动设备研发高性能电源管理芯片。2014年8月加入南方科技大学担任助理教授，2019年12月获晋升为副教授。詹陈长教授长期从事模拟、混合信号和电源管理集成路与系统的分析和设计。迄今为止发表了1本专著及>70篇SCI/EI学术论文，已获授权8项中国专利、5项美国专利。詹教授获得过IEEE ISIC'2009和EDSSC'2018最佳论文奖、IEEE EDSSC'2010最佳学生论文奖、IEEE ISCAS'2011最佳学生论文奖、南方科技大学2018年度优秀青年科研奖、2019年度优秀教学奖、优秀书院导师奖以及2020年度五年贡献服务奖。他是IEEE APCCAS'2014的审稿委员会成员、IEEE ICTA'2018、ICTA'2019和ICTA'2020的技术程序委员会成员、 Hindawi APEC期刊客座编辑、IEEE ISCAS'2018, ISCAS'2019以及 ICTA'2018的分会场主席/共同主席，同时他还担任集成电路领域众多国际知名期刊和会议的特邀审稿人。他是IEEE高级会员。
联系方式：zhancc@sustech.edu.cn

教育经历
2007-2011，香港科技大学电子及计算机工程学，博士
2004-2007，复旦大学微电子学及固体电子学，硕士
2000-2004，复旦大学电子信息科学与技术，学士


工作经历
2019-至今， 南方科技大学，副教授
2014-2019， 南方科技大学，助理教授
2012-2014， 美国高通公司，高级工程师
2011-2012 ，香港科技大学，博士后研究员
2006-2007 ，上海芯原微电子，实习模拟电路设计工程师


研究简介
电源管理、能量收集集成电路与系统
模拟与混合信号集成电路
低功耗集成电路设计方法
ResearcherID链接: https://publons.com/researcher/**/chenchang-zhan/
Google Scholar链接: https://scholar.google.com/citations?user=tYZ863gAAAAJ&hl=en


所获荣誉
2020，南方科技大学“五年贡献服务奖”
2019，获晋升为IEEE Senior Member
2019，南方科技大学“优秀教学奖”
2019，南方科技大学“优秀书院导师奖”
2018，南方科技大学“优秀青年科研奖”
2018，IEEE EDSSC最佳论文奖
2017，南方科技大学首届创新创业大赛“优秀导师”
2016，第六届全国大学生集成电路设计大赛“优秀指导教师”
2016，南方科技大学“招生工作先进个人”
2016，南方科技大学树仁书院“年度导师”
2016，广东省深圳市南山区“领航人才”C类
2014，广东省深圳市海外高层次“孔雀计划”人才C类
2011，IEEE ISCAS最佳学生论文奖
2010，IEEE EDSSC最佳学生论文奖
2009，IEEE ISIC最佳论文奖
2009，IEEE ISCAS最佳论文奖提名

代表文章
Q. Huang, C. Zhan, and J. Burm, "A 4-MHz digitally controlled voltage-mode buck converter with embedded transient improvement using delay line control techniques," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 67, no. 11, pp. 4029-4040, Nov. 2020. https://doi.org/10.1109/TCSI.2020.**.

L. Wang and C. Zhan, “1V relaxation oscillator with integrated voltage and current reference,” IET Elec. Letters, vol. 56, no. 20, pp. 1035-1036, Sept. 2020. https://doi.org/10.1049/el.2020.1855.

Q. Huang, C. Zhan, L. Wang, Z. Li and Q. Pan, "A -40 oC to 120 oC, 169 ppm/oC nano-Ampere CMOS current reference," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 67, no. 9, pp. 1494-1498, Sept. 2020. https://doi.org/10.1109/TCSII.2020.**.

J. Lin, L. Wang, Y. Lu and C. Zhan, "A nano-watt dual-output subthreshold CMOS voltage reference," IEEE Open J. Circ. Syst., vol. 1, pp. 100-106, Aug. 2020. https://doi.org/10.1109/OJCAS.2020.**.

J. Lin, L. Wang, C. Zhan and Y. Lu, "A 1-nW Ultra-Low Voltage High PSRR Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no.10, pp. 1653-1657, Oct. 2019. https://doi.org/10.1109/TCSII.2019.**.

G. Cai, C. Zhan and Y. Lu, “A fast-transient-response fully-integrated digital LDO with adaptive current step size control,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3610-3619, Sept. 2019. https://doi.org/10.1109/TCSI.2019.**.

L. Wang and C. Zhan, “A 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3457-3466, Sept. 2019. https://doi.org/10.1109/TCSI.2019.**.

Y. Tan, C. Zhan and G. Wang, "A fully-on-chip analog low-dropout regulator with negative charge pump for low-voltage applications," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no. 8, pp. 1361-1365, Aug. 2019. https://doi.org/10.1109/TCSII.2018.**.

C. Zhan, G. Cai and W. H. Ki, “A transient-enhanced output-capacitor-free low-dropout regulator with dynamic miller compensation,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 243-247, Jan. 2019. https://doi.org/10.1109/TVLSI.2018.**.

H. Li, C. Zhan and N. Zhang, "A fully-on-chip digitally assisted LDO regulator with improved regulation and transient responses," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 65, no. 11, pp. 4027-4034, Nov. 2018. https://doi.org/10.1109/TCSI.2018.**.

Q. Huang, C. Zhan, and J. Burm, “A 30 MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 11, pp. 1659-1663, Nov. 2018. https://doi.org/10.1109/TCSII.2017.**.

L. Wang, C. Zhan, J. Tang, Y. Liu and G. Li, “A 0.9V 33.7ppm/oC 85nW sub-bandgap voltage reference consisting of subthreshold MOSFETs and single BJT,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2190-2194, Oct. 2018. https://doi.org/10.1109/TVLSI.2018.**.

C. Huang, C. Zhan, L. He, L. Wang and Y. Nan, "A 0.6V-minimum-supply, 23.5ppm/oC subthreshold CMOS voltage reference with 0.45% variation coefficient," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 10, pp. 1290-1294, Oct. 2018. https://doi.org/10.1109/TCSII.2018.**.

Y. Liu, C. Zhan, L. Wang, J. Tang and G. Wang, “A 0.4-V wide temperature range all-MOSFET subthreshold voltage reference with 0.027%/V line sensitivity,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 8, pp. 969-973, Aug. 2018. https://doi.org/10.1109/TCSII.2018.**.

L. Wang, C. Zhan, J. Tang and G. Li, “An amplifier-offset-insensitive and high PSRR subthreshold CMOS voltage reference.” Int’l J. Circ. Theor. Appl., vol. 46, no. 2, pp. 259-271, Feb. 2018. https://doi.org/10.1002/cta.2383.

S. Zhao, C. Zhan and G. Cai, “A 2×VDD-enabled output-capacitor-free low-dropout regulator with fast transient response for low-cost system-on-chip,” J. Circ. Syst. Comp., vol. 27, no.9, pp. **-1-17, Jan. 2018. https://doi.org/10.1142/S02**438.

Y. Liu, C. Zhan and L. Wang, “An ultralow power subthreshold CMOS voltage reference without requiring resistors or BJTs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 26, no. 1, pp. 201-205, Jan. 2018. https://doi.org/10.1109/TVLSI.2017.**.

Q. Huang, C. Zhan and J. Burm, “A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector,” Microelectronics Journal, vol. 67, pp. 19-24, Sept. 2017. https://doi.org/10.1016/j.mejo.2017.07.004.

L. Wang, C. Zhan, J. Tang, S. Zhao, G. Cai, Y. Liu, Q. Huang and G. Li, “Analysis and design of a current-mode bandgap reference with high power supply ripple rejection,” Microelectronics Journal, vol. 68, pp. 7-13, Aug. 2017. https://doi.org/10.1016/j.mejo.2017.08.011.

Q. Huang, H. Joo, J. Kim, C. Zhan and J. Burm, “An energy-efficient frequency domain CMOS temperature sensor with switched Vernier time-to-digital conversion,” IEEE Sensors Journal, vol. 17, no. 10, pp. 3001-3011, May 2017. https://doi.org/10.1109/JSEN.2017.**.