摘要:在芯片设计领域，采用模型驱动的FPGA设计方法是目前较为安全可靠的一种方法.但是，基于模型驱动的FPGA设计需要证明FPGA设计模型和生成Verilog/VHDL代码的一致性；同时，芯片设计的正确性、可靠性和安全性也至关重要.目前，多采用仿真方法对模型和代码的一致性进行验证，很难保证设计的可靠性和安全性，并存在验证效率低、工作量大等问题.提出一种新型验证设计模型和生成代码一致性的方法，该方法利用MSVL语言进行系统建模，并通过模型提取命题投影时序逻辑公式描述的系统的性质，通过统一模型检测的原理，验证模型是否满足性质的有效性.进而，应用信号灯控制电路系统作为验证实例，对验证方法做了检验和说明.



Abstract:In the field of chip design, the use of model-driven FPGA design methods is currently a safer and more reliable method. However, model-driven FPGA design needs to prove the consistency of the FPGA design model and the generated Verilog/VHDL code. Further, the chip design correctness, performance, reliability, and safety are critical. At present, simulation methods are often used to verify the consistency of models and codes. It is difficult to ensure the reliability and safety of the design, and there are problems such as low verification efficiency and heavy workload. This study proposes a new method to verify the consistency of the design model and the generated code. This method uses the MSVL language to model the system, and propositional projection temporal logic (PPTL) formula to describe the properties of the system, then based on the principle of unified model checking, verifies whether the model meets the validity of the property. Furthermore, a signal light control system is used as a verification example to verify and explain the verification method.



PDF全文下载地址:

http://jos.org.cn/jos/article/pdf/6250