摘要:近年来，卷积神经网络（CNN）在图像识别和分类领域的高精度表现使其在机器学习领域受到了广泛关注.然而CNN的计算与访存密集特性给需要支持各种负载的通用处理器带来了巨大压力.因此，涌现了大量CNN专用硬件加速器.它们虽然提高了效率但却缺乏灵活性.基于新兴的RISC-V架构设计了包含10条矩阵指令的专用指令集RV-CNN.通过抽象典型CNN中的计算为指令，该指令集可灵活支持CNN推理过程并具有比通用ISA更高的代码密度.在此基础上，提出了代码至指令的映射机制.通过在Xilinx ZC702上使用该指令集构建不同网络模型后发现，相比于x86处理器，RV-CNN平均具有141倍的能效和8.91倍的代码密度；相比于GPU，平均具有1.25倍的能效和1.95倍的代码密度.另外，相比于以往的CNN加速器，该设计在支持典型CNN模型的同时仍具有不错的能效.



Abstract:In recent years, due to the high-accuracy performance of Convolutional Neural Network (CNN) in character recognition and image classification, it has received widespread attention in the field of machine learning. Nevertheless, the compute-intensive and memory-intensive characteristics of CNN have posed huge challenges to the general-purpose processor, which needs to support various workloads. Therefore, a large number of CNN-specific hardware accelerators have emerged to improve efficiency. Whereas, although previous accelerators are significantly efficient, they usually lack flexibility. In this study, classical CNN models are analyzed and a domain-specific instruction set of 10 matrix instructions, called RV-CNN, is design based on the promising RISC-V architecture. By abstracting CNN computation into instructions, the proposed design can provide sufficient flexibility for CNN and possesses a higher code density than the general ISA. Based on this, a code-to-instruction mapping mechanism is proposed. By using the RV-CNN to build different CNN models on the Xilinx ZC702, it was found that compared to x86 processors, RV-CNN has an average of 141 times energy efficiency and 8.91 times the code density; compared to GPU, it has an average of 1.25 times energy efficiency and 1.95 times the code density. Besides, compared to previous CNN accelerators, the design supports typical CNN models while having good energy efficiency.



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