1.
Introduction
Negative capacitance field-effect transistors (NC FETs) have been widely investigated in recent years as a powerful alternative for low-power and high-performance circuits due to their ultra-steep subthreshold characteristics and compatibility with traditional complementary metal–oxide–semiconductor (CMOS) processes[1-7]. To date, negative capacitance devices based on planar or 3D FinFET structures have been reported by many researchers, and most of them characterize the device performance in view of their direct-current (DC) characteristics, including ID–VG and ID–VD, etc.[8-13]. These characteristics are often used as the major determinant of speed and power performance in integrated circuits. However, many transient and short time responses need to be investigated to complete the DC characteristics, because of the self-heating effect[14], the body charge effect[15] and charge trapping[16] in the gate dielectric can attenuate the current in the DC case compared with the intrinsic transient current of the transistors. Therefore, transient response measurement of short pulses can better reflect the actual performance of NC FETs in the logic circuits. On the other hand, the current reported experimental results for the frequency domain performance study of NCFETs are controversial. Salahuddin et al. has demonstrated from theory to single transistors to circuit level that NC FETs have a high-frequency performance comparable to conventional devices[17-20]. However, Kobayashi et al. argue that NC devices cannot operate in the frequency domain beyond 1 MHz[21, 22], and the experimental results of Zhou et al. also show that the device performance degrades under the condition of the 1 μs pulse width of the gate signal[23]. Therefore, the frequency response of NC devices needs to be further investigated. Commercial equipment such as the 4200 Vector Network Analyzer can measure the transient characteristics of devices under pulse conditions, but these methods are complex or cannot measure pulse currents under very short conditions[24-26]. A simpler, faster and cheaper approach to characterize the intrinsic transient properties of NC FinFETs needs to be proposed.
In this paper, based on our fabricated high-performance HZO NC FinFET, two measurement platforms based on an oscilloscope and arbitrary wave function generator were built in order to characterize the transient characteristics of the NC FinFET. The conventional resistive load inverter test scheme can characterize the transient characteristics of the device, however, there are significant high-frequency limitations, and the frequency domain can be characterized within 100 kHz. Furthermore, the transient response in the higher frequency domain can be measured by using an oscilloscope connected directly to the source of the device as a ground. The scheme eliminates the effect of load resistance and can measure the transient current response at pulse widths as low as 5 ns.
2.
Experiment and method
Fig. 1(a) shows the fabrication flow of the HZO NC FinFET, which is similar to our previous work[7]. Fig. 1(b) shows the cross-sectional TEM image of Fin. It can be seen that multilayer HKMGs are highly conformal and uniform. The thicknesses of the interface layer (IL) and ferroelectric layer (FE) are 1 and 3 nm, respectively. Two kinds of test circuit were built to investigate the transient response of NC FinFETs, as is shown in Figs. 1(c) and 1(d), respectively. In Fig. 1(c), a load resistor RL was chosen without inductance (Nevertheless, non-inductive is not absolutely non-inductive, and the larger the resistance, the greater the relative inductance itself). The specific test principle of the resistive load inverter test scheme is as follows: when the transistor is disconnected, the operation voltage VDD loading directly to the oscilloscope through RL, and the voltage displayed by the oscilloscope is the operation voltage VDD. When the device is on, the source and drain is on, which is equivalent to the source drain resistance in parallel with the internal resistance of the oscilloscope and then in the series with the load resistor, at this time,
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Figure1.
(Color online) (a) The fabrication flow of the fabrication of NC FinFET. (b) Cross-sectional TEM image of the NC FinFET device. (c) Schematic diagram of the resistive load inverter characterization single-transistor frequency characteristics test circuit. (d) Schematic diagram of the optimization measurement scheme.
$$ {V}_{ m{out}}={V}_{ m{osc}}={V}_{ m{DD}}-{I}_{ m{DS}}{R}_{ m{L}}. $$  |
Here the internal resistance of the oscilloscope selects 1 MΩ, which is much larger than the on resistance of the transistor, so the shunt effect of the oscilloscope could be ignored. The frequency characteristics of the transistor can be studied by monitoring the change in Vout, when keeping the drain voltage VDD constant, and only changing the pulse width of the applied gate signals. Theoretically, if high-frequency characteristics of the device deteriorate as the pulse width decreases, the on-current of the device will decrease under the same gate and drain voltages. Meanwhile, the corresponding Vout will increase and the high-frequency characteristics can be characterized in this way. Furthermore, the optimization of the measurement scheme is shown in Fig. 1(d) and will be explained later in detail.
3.
Results and discussion
3.1
Frequency response of NC FinFETs based on load resistance inverter measurements
In the experiment, the applied gate pulse amplitude is set to 0.8 V, the pulse width was adjusted according to the actual experimental needs (the drain voltage VDD = 0.8 V, RL = 100 kΩ). Fig. 2 shows the measured Vout in our experiment with different frequencies. As shown in Fig. 2(a), the output signal is a rectangular wave with an amplitude of 0.26 V under an applied VGS of 1 ms pulse width (corresponding to frequency 0.5 kHz), and there is large discrimination between the high and low levels of the output voltage. However, the output signal is no longer a complete rectangular pulse signal when the gate pulse frequency increases to 5 kHz (Fig. 2(b)). Therefore, the frequency characteristics of the device may be studied by changing the gate pulse frequency in a not high frequency domain.
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Figure2.
(Color online) Real-time output data of the load-resistance based inverter measurement, with the gate pulse width (a) 1 ms, and (b) 10 μs, respectively.
Fig. 3 shows the measured output voltage as a function of gate pulse frequencies and the device used is a conventional NMOS FinFET. When the gate pulse frequency is higher than 100 kHz, the output voltage (Vout) began to gradually increase, indicating that the on-state current of the device gradually reduced with pulse width below 10 μs. The results indicating the performance of the device may degrade at high-frequency conditions. After analyzing the specific data, we suspect that the variation of output voltage in this test scheme may be mainly the effect of the capacitive resistance of the load resistor rather than the degradation of device performance, because our manufacture conventional devices with high frequency performance at least in the MHz frequency domain theoretically. Therefore, to test our suspicionsa, a 5 V pulse signal was sent on the load resistance directly connected to the oscilloscope in varies frequencies. The test results show that the signal on the oscilloscope exhibits serious distortion when the applied pulse width is shorter than 10 μs, as shown in Figs. 4(a) and 4(b), respectively. So the measured results shown using the above resistor-loaded inverter do not truly reflect the high-frequency performance of the transistor. In addition, the load resistor resistance in this scheme requires the load resistor to have good high-frequency characteristics and comparable to the device on-resistance or much larger than the on-resistance (generally several tens of kΩ level). Then the oscilloscope shows the voltage of the device in the on state and the voltage in the off state will be obviously different.
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Figure3.
(Color online) Experimentally measured output voltage as a function of the applied gate signal frequencies.
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Figure4.
Waveforms of different frequencies displayed directly on the oscilloscope after resistive loading, (a)10 kHz and (b) 100 kHz.
A large resistance value and good high-frequency performance of the resistor could not be achieved (a high-frequency test in general load resistance value of 50 Ω) because the larger the impedance value, the greater the capacitive resistance. Therefore, the test scheme needs to be optimized in order to further study the high-frequency performance based on a single transistor.
3.2
Frequency response with optimization measurement for single-NC Fin-FETs
In order to eliminate the influence of load resistance effect, an optimized measurement scheme based on a single transistor was proposed and carried out, as shown in Fig. 1(d). In this scheme, both the signal generator and oscilloscope internal resistance were set to 50 Ω impedance, and the oscilloscope was directly connected to the source of the device, i.e., connecting the source of the device directly to the 50 Ω impedance channel of the oscilloscope, and the drain current can be calculated directly by the following equation:
$$ {I}_{ m{DS}}=frac{{V}_{ m{OSC}}}{{R}_{0}}. $$  |
R0 = 50 Ω represents the impedance of the oscilloscope. This scheme excludes the influence of load resistance and sets the waveform of the pulse string loaded on the gate to take a point every 0.05 V from 0.05 to 1 V, with a total of 20 pulses in one pulse string cycle. The width of each pulse can be controlled by setting the individual pulse string time, and then the Id–Vg curves of different amplitudes and pulse widths are measured out. The sub-threshold slope (SS), hysteresis, threshold voltage (Vt) and drain-induced barrier lowering (DIBL) can then be extracted for the corresponding pulse width to fully analyze the frequency characteristics of the device. The measured single-transistor real-time results were directly carried out, shown in Fig. 5. Under the 1 μs pulse width, when the gate voltage is greater than 0.3 V (a PMOS device used here, the on-state voltage is negative voltage region) we can accurately extract the on-state current. However, when the gate voltage is lower than 0.3 V, the on-state current is too small (at this time, the nA level current is about 0.5 μV magnitude on the oscilloscope), and the oscilloscope vertical axis resolution is not enough (resolution has been adjusted to the highest). Therefore, the program can be studied by measuring the on-state IDS to its frequency characteristics. The test conditions are set to VGS = VDD = 1 V for NMOS (–1 V for PMOS), and the gate pulse widths are 10 ms, 1 ms, 100 μs, 10 μs, 1 μs, and only the variation of the IDS in the on-state with frequency is studied.
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Figure5.
(Color online) The measured real-time pulse train on-current of single-transistor.
Figs. 6(a) and 6(b) show the experimentally measured transient pulse current at pulse widths of 10 ms and 1 μs, when VGS = VDD = –1 V. The frequency characteristics of the device by characterizing the variation of the pulse current with the gate pulse width were characterized. The results show that the pulse width is as short as the order of μs, and the measured current signal is still very clear, which is more credible than those of the resistive load test scheme.
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Figure6.
(Color online) Measured transient currents of the single transistor, (a) with 10 ms pulse width, (b) with 1 μs pulse width, (c) variation of the extracted on-state currents of the single-transistor with frequency at different gate voltages.
Fig. 6(c) shows the variation of the transient on-state current with pulse width measured in the experiment. It can be seen that with the gradual decrease of the gate pulse width, the on-state current of the device does not change significantly in the frequency range of 1 MHz, for all three gate voltage conditions. The results show that the device in the 1 MHz frequency range and the on-state current does not affect the frequency, which indicated that the NC FinFET can work at 1 MHz frequency and the on-state current does not significantly degrade. Nonetheless, the scheme is indeed also not a complete characterization of the IDS–VGS curve at high frequencies, but it can also characterize the device's high-frequency characteristics to some extent, because the on-current does not vary with the gate frequency. Therefore, we continued to reduce the pulse width on the basis of 1 MHz and studied in depth the variation of the on-state current of a single NC FinFET with a minimum pulse width measured to 5 ns.
Fig. 7 shows the experimentally measured on-current with a pulse width of 100 ns. The discrimination between high and low levels is obvious under this test scheme, and the off-state noise is small, so the transient on-current of the device can be clearly measured.
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Figure7.
(Color online) Real-time test results of on-state IDS of the NC FinFET.
Fig. 8 summarizes the frequency test results for NMOS and PMOS devices, the red and blue curves represent NC FinFETs and conventional HfO2 FinFETs, respectively. The results show that the on-current of both devices does not vary with the gate signal pulse width. However, the on-current of both devices shows a trend to become larger with the gate voltage pulse width gradually below 100 ns, which seems to contradict the theory of conventional MOSFETs. In fact, the FinFET gate interface layer is not an ideal interface, including some defects and traps, and the phenomenon can be explained by the fast trap effect[27, 28]. When the gate voltage rises fast enough, the empty space is not filled due to the moment of applied voltage, the transient electron concentration in the channel is higher than the DC case at this time, thus generating a transient high current. But after the rising edge time of the pulse, the electrons will continue to be trapped by the trap, leading to a degradation of the current, i.e., exhibiting a current reduction. The phenomenon also indicates that the trap charge at the gate interface contributes to the on-state current of the device at high frequencies.
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Figure8.
(Color online) Experimentally measured variation of the on-state current with pulse width for NC FinFET and conventional FinFET. (a) NMOS. (b) PMOS.
More importantly, under the same conditions, the measured on-state current of the NC FinFET is consistently greater than those of the conventional FinFET (about 80% @ NMOS and almost equal @ PMOS), and a gate voltage pulse width of 5 ns is demonstrated using this approach, indicating that the NC FinFET also has an advantage over the conventional device in terms of drive current for high frequency applications, which is may be attributed to the inherent charge gain effect of the ferroelectric material[28]. The polarization reversal of the ferroelectric material adds an additional portion of charge to the channel and increases the on-state current.
4.
Conclusion
In summary, the frequency characteristics based on single-NC FinFET are systematically investigated by two self-built test schemes. The conventional resistive load invertor test solution can only characterize the frequency characteristics in the low-frequency domain. However, the optimized solution test scheme of single transistor shows that the on-state current does not significantly change in the 1 MHz frequency domain. Further high-frequency test results show that NC FinFETs and conventional FinFETs start to show a trend of larger on-currents when the gate voltage pulse width is less than 100 ns, which is attributed to the defect effect of the device interface layer. Furthermore, NC FinFETs exhibit a larger on-current than that of the conventional FinFETs, which is related to the charge gain of ferroelectric materials. The overall experimental results show that NC FinFETs have a high-frequency performance in terms of on-state current that is not weaker than that of conventional FinFETs, and the current driving capability is better than that of conventional devices, which is an important impetus for future research on the high-frequency characteristics of NC FinFETs.
Acknowledgements
This project was supported in part by the Science and Technology program of Beijing Municipal Science and Technology Commission under grant Z201100006820084, in part by the National Natural Science Foundation of China (NSFC) under grants 92064003, 61904194, 91964202 and 61874135, in part by the Youth Innovation Promotion Association, Chinese Academy of Sciences under grants Y9YQ01R004 and Y2020037, in part by the Opening Project of Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences under grants E0YS01X001 and E0290X03.
