1.
Introduction

An ISM band at 245 GHz is available in Europe, which could be used for imaging radar^{[1, 2]}, security applications, bio-medical sensors for medical diagnostics, mm-wave gas spectroscopy^[3–6], as well as communication^[7–9].



A subharmonic receiver for 245 GHz spectroscopy sensor applications is presented in this paper. The requirements for the 245 GHz receiver are low power, wide bandwidth, high linearity, and high integration level with integrated LO signals for easy implementation in PCB level design with external PLL.



The continuously increasing demand on the required operational bandwidth drives the operation frequencies into the millimeter-wave (mm wave) and submillimeter wave frequency range. Traditional mm Wave equipment mostly relies on technologies like Schottky diodes or III–V monolithic integrated circuits^[2]. In Ref. [10], a monolithic 60 GHz balanced amplifier with a gain of 20 dB is presented using 0.15 μm GaAs pHEMT technology. In Ref. [11], a W-band two-stage cascade amplifier with a gain of 25.7 dB in InP HEMT technology is reported. In Ref. [12], W-band quartz based fixed tuned doublers with the highest output power of 29.5 mW are designed with planar Schottky diodes. Recently, silicon technologies like CMOS or BiCMOS technology, on the contrary, undergoing steady scaling, have been shown to be a promising substitution of traditional technologies in mm wave circuit design in the frequency range below 300 GHz or even beyond^[2]. In Ref. [13], a three-stage cascade LNA with a gain of 17.3 dB is achieved in 65-nm CMOS technology. In Ref. [1] a fully differential 220 GHz integrated receiver front-end without VCO for imaging has been demonstrated in SiGe technology. Both the LNA and the mixer are implemented with differential signaling. In Refs. [3, 4], a receiver consisting of a 245 GHz folded dipole antenna, a 245 GHz differential transformer coupled LNA, a Gilbert-cell based subharmonic mixer (SHM), and a 120 GHz VCO-divider chain is presented for 245 GHz gas spectroscopy applications. The same 245 GHz receiver is well utilized in a 245 GHz gas sensor^[5] and gas spectroscopy system for breath analysis^[6]. In Ref. [7], a fully-integrated differential direct conversion mixer-first quadrature receiver chip composed of ×16 multiplier chain, IQ mixer, PA, quadrature coupler, and on-chip antenna working at 240 GHz for communication is given. In Ref. [8], a fully integrated differential direct-conversion quadrature receiver at 240 GHz composed of ×16 multiplier chain, IQ mixer, PA, LNA, and on-chip antenna for communication is presented. In Ref. [2], a monolithically integrated differential 210–270 GHz FMCW radar transceiver for imaging is reported. Although differential signaling is more robust to common-mode noise^[1–8], it comes at the expense of higher power and more complicated LO distributions. In Ref. [9], in order to realize a wide bandwidth receiver for communication, a TIA receiver is designed. In Ref. [14], to reduce power dissipation, a subharmonic receiver comprised of a single-ended CB LNA and a 2nd transconductance SHM is studied in this paper.



In this work, in order to achieve high gain, low power, high linearity, and low noise figure, a subharmonic receiver based on a single-ended 245 GHz CB LNA, a 2nd transconductance SHM and 120 GHz VCO is studied and presented. Integrated with on-chip antenna, the receiver is measured on-chip with an external 245 GHz transmitting power source. The receiver will be utilized in a gas spectroscopy sensor system, in which an absorption cell containing methanol (CH₃OH) will be placed between the 245 GHz transmitter and 245 GHz receiver to measure the absorption spectrum of methanol^[15]. This frequency region was chosen, because many volatile organic compounds and toxic industrial chemicals have characteristic fingerprint-like absorption spectra around 250 GHz^[16].

2.
Circuit design of the 245 GHz 2nd transconductance receiver with on-chip antenna

Fig. 1 presents the architecture of the 245 GHz 2nd transconductance receiver with on-chip antenna. The chip consists of a 245 GHz folded dipole antenna, a 245 GHz 4 stage CB LNA, a 2nd transconductance subharmonic mixer, and a 120 GHz push-push VCO with a 1/64 divider. The 1/64 divider is included for easy implementation in PCB level design with external PLL in future for the gas sensor application.






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Figure1.
Topology of the subharmonic receiver with on-chip antenna.




Fig. 2 shows the detailed circuit schematics of one stage of the 4 stage 245 GHz CB LNA, 2nd transconductance subharmonic mixer, and 120 GHz push-push VCO^[14].



In Fig. 2(a), V_cb provides the base bias for the common base transistor through diode-connected transistor D1 and resistor R₁. Transmission lines TL_sh not only provide the DC ground for the emitters of the transistors but as well work together with the TL_ser and metal–insulator–metal (MIM) capacitors Cn (n = 1–4) to form the input and inter-stage impedance matching network. Transmission lines TL_load are inductive loads for each common base stage. C_byp provides the AC ground for the base connection and the DC supply. Bondpad capacitances are included in both the input and output matching networks.



In Fig. 2(b), a schematic of the 245 GHz subharmonic mixer is shown. Q1, Q2 are the mixer core and they are biased close to the turn-on voltage in order to maximize the nonlinearity characteristic of the transistors^[9]. Resistor ladders are utilized for the Q1, Q2 biasing. Two parallel shunt-series stub transmission line structures are used to achieve isolation between the LO and RF ports. A quarter wavelength @ LO open shunt stub and a quarter wavelength @ LO series stub form an open impedance at LO frequency. A quarter wavelength @ RF open shunt stub and a quarter wavelength @ RF series stub form an open impedance at RF frequency. The two transmission lines T1 and T2 are used to provide 90 degree phase delay at 245 GHz and the whole input network makes the RF signals become out of phase while the LO signals are kept in phase at the input of the transistors. After the mixer stage, a differential common emitter buffer stage is utilized as the output buffer stage to provide impedance matching to 50 Ω. 50 Ω resistive loads are used in the buffer for output matching. A capacitor is placed between the mixer and buffer stage for DC blocking. For the buffer stage transistors Q3, Q4 work in the amplifying region and enough headroom is ensured at output for high linearity.



In Fig. 2(c), a schematic of the oscillator is presented. The oscillator has to provide a 120 GHz single-ended signal to the 2nd transconductance SHM. To fulfill all requirements in terms of tuning range, power and reliability, a push-push oscillator topology is chosen^[17]. With this topology, it is possible to provide a signal path with relatively low fundamental frequency f₀ of 60 GHz to the frequency divider and to provide the 120 GHz signal via a buffer to the 2nd transconductance SHM.



At the interface of the RF port of the 2nd transconductive SHM and the RF output of LNA, conjugate matching is implemented between the output of LNA and the RF port of the SHM for maximum power transfer. At the interface of the LO port of SHM and the LO port of VCO, both ports are impedance matched to 50 Ω firstly and then connected directly. At the interface of on-chip antenna and the RF input of LNA, both ports are impedance matched to 50 Ω firstly as well and then connected directly.



Fig. 3 is the chip photo of the 245 GHz 2nd subharmonic receiver with on-chip antenna with each circuit block indicated in the figure.






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Figure3.
(Color?online) Chip photo of the 2nd transconductance subharmonic receiver with on-chip antenna.

3.
Measurement results of circuit blocks and on chip measurement results of the receiver integrated with on-chip antenna with external 245 GHz power source

The CB LNA, 120 GHz VCO, LNA-VCO chain, and the on-chip antenna were designed as separate components and measured^{[14, 18]}.



Fig. 4 presents the CB LNA with a 3-dB bandwidth extending from 237 to 261 GHz. A gain of 11 dB is achieved at 243 GHz, and the simulated NF is 12 dB.






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Figure4.
S₂₁ of CB LNA.




In Fig. 5, the VCO-frequency changes from 116.9 to 126.4 GHz by increasing the tuning voltage V_tune from 0 to 3 V. An output power of ?1 dBm is measured at 122 GHz, and a phase noise of –88 dBc/Hz at 1 MHz offset is measured at V_tune of 1.3 V with the corresponding LO frequency of 122 GHz; the phase noise of ?96 dBc/Hz at 1 MHz offset is measured at V_tune of 0 V.






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Figure5.
Output power of the LO signal versus LO frequency.




Fig. 6 shows the simulation and measured conversion gain of the receiver versus RF frequency, with fixed VCO tuning voltage (V_tune: 1.3 V), which corresponds to an LO frequency of 122 GHz. Measurement results agree with the simulation results. The receiver achieves 15 dB peak-conversion gain in the lower side band (< 244 GHz) with the 3-dB lower RF frequency bandwidth extending from 242.5 to 243.8 GHz; and it reaches 14 dB peak conversion gain in the upper side band (> 244 GHz) with the 3-dB RF frequency bandwidth extending from 244.03 to 245.9 GHz. The limited IF bandwidth is due to the filtering of capacitorsC_P (400 fF) in parallel with the load resistors R_L in the 2nd SHM as shown in Fig. 2. In Fig. 6, the conversion gain drops when RF frequency approaches 244 GHz due to the decoupling capacitors between the mixing core and the output buffer stage. The 2nd transconductance SHM contributes 3.3 dB gain in the receiver, which is calculated from the difference between the conversion gain of the receiver and the gain of the LNA. Fig. 6 also presents the conversion gain of the receiver with fixed IF frequency at 1 GHz. In this case, LO frequency is swept from 116.9 to 126.4 GHz (tuning voltage from 0 to 3 V). The input RF frequency is swept simultaneously to keep the IF frequency constant at 1 GHz. The receiver achieves 3-dB RF frequency bandwidth extending from 241 to 256 GHz, with a 15 GHz 3-dB bandwidth.






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Figure2.
Schematics of (a) one stage of the 4 stage 245 GHz CB LNA, (b) 2nd transconductance SHM, and (c) 120 GHz VCO.






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Figure6.
(Color?online) Conversion gain of the LNA-SHM chain versus RF frequency.




An on-chip 245 GHz antenna composed of two half-wavelength folded dipoles was designed with LBE technology (localized backside etching). Fig. 7 presents the comparison between the simulated gain and measured gain of the antenna ^[18]. Around 6–7 dBi antenna gain is estimated at 245 GHz.






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Figure7.
(Color?online) The comparison between measured and simulated gain of the on-chip antenna.




On chip measurement of the 2nd transconductance subharmonic receiver with integrated antenna is performed. Fig. 8 is a photo of the setup of the measurement.






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Figure8.
(Color?online) A photo of the on-chip measurement of subharmonic receivers with antenna.




The diced chips of the subharmonic receiver with on-chip antenna is glued on an FR-4 board in order to perform on chip measurements. Frequency extender ZVA-Z325 is working as a frequency up converter and feeds the up converted 245 GHz RF signals into a standard WR-3.4 horn antenna. The horn antenna transmits power towards the glued diced receiver chip. The diced receiver chip receives 245 GHz RF signal through the on-chip antenna, down converts the RF signal and gets the IF signals. Fig. 9 shows more details upon equipment setup. FSV3Q is a frequency spectrum analyzer.






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Figure9.
Details upon setup of the on-chip measurement of subharmonic receivers with antenna.




Using the setup mentioned above, with IF frequency fixed at 250 MHz, the IF output power is measured. According to Friis power transmission Eq. (1), where P_t is transmit power, G_t and G_r are the transmit and receive antenna gain, and R is the distance between antennas, where λ is wave length, the power link could be calculated.

${P_{ m{r}}} = {P_{ m{t}}}frac{{{G_{ m{t}}}{G_{ m{r}}}{lambda ^2}}}{{{{left( {4pi R} ight)}^2}}}.$

(1)

Assuming G_t of the horn antenna is 20 dBi, G_r is 7 dBi, the distance between the horn antenna and the chip is 10 cm, according to Eq. (1), and the received RF power P_r is P_t ? 33.22 dBm. Accordingly, the conversion gain of the receiver can be obtained by subtraction P_r dBm from the received IF signal power. The results are as shown in Fig. 10. Integrated with on-chip antenna, the receiver is measured on chip with a conversion gain of 15 dB and a bandwidth of 15 GHz with a low power dissipation of 288 mW. In Fig. 10, conversion gain remains almost in 4-dB bandwidth in the frequency between 245 and 260 GHz, except for at 2 frequency points conversion gain dips suddenly below 10 dB. The sudden dipping might be due to multi-path loss of the RF signals. Table 1 shows the performance of the chip.






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Figure10.
Calculated conversion gain of receiver integrated with on-chip antenna.

Parameter	Value
CB LNA	25 mA at 2 V
SHM	17 mA at 3 V
VCO	32 mA at 3.3 V
Divider	29.5 at 3 V
Total power dissipation	288 mW
Antenna gain[18]	7 dBi at 245 GHz
NF[14]	17 dB
Input referred 1 dB compression point[14]	?24 dBm
Conversion gain	15 dB at 245 GHz
RF bandwidth	15 GHz

Table1.
Performance of the receiver.



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Parameter	Value
CB LNA	25 mA at 2 V
SHM	17 mA at 3 V
VCO	32 mA at 3.3 V
Divider	29.5 at 3 V
Total power dissipation	288 mW
Antenna gain[18]	7 dBi at 245 GHz
NF[14]	17 dB
Input referred 1 dB compression point[14]	?24 dBm
Conversion gain	15 dB at 245 GHz
RF bandwidth	15 GHz

Adding up separate components measurement results, e.g. the conversion gain of the LNA-mixer chain (14 dB) and on-chip antenna gain (6–7 dBi), the subharmonic receiver with an integrated antenna should achieve an ideal conversion gain of 20–21 dB in total. Comparing the conversion gain (15 dB) of the 2nd subharmonic receiver with integrated on-chip antenna with the ideal conversion gain (20–21 dB), the conversion gain of the receiver in this work is 5–6 dB less than the ideal value. The loss in conversion gain might be attributed to the multi-path loss of RF signals, errors in calibration of in measurements of the system, and so on.



Table 2 presents a performance comparison of the receiver in this work with a state-of-the-art one. Comparing the receiver in this work with receivers in Refs. [1, 3, 4], comparable performance is achieved but with much lower power. Compared with the receiver in Ref. [1], the receiver in this work with VCO and divider consumes only 107 mW, which is merely half of that in Ref. [1]. Compared with the receivers in Refs. [3, 4], both receivers include circuit blocks of on-chip antenna, 120 GHz VCO, and divider, a comparable performance is achieved, but the power dissipation of the receiver in this work is less than half of that in Refs. [3, 4]. Comparing this work with the receiver in Ref. [9], a 55 GHz wide bandwidth is obtained with the TIA receiver architecture in Ref. [9], but the LO source is provided off-chip in Ref. [9], and the power dissipation of Ref. [9] is almost two times of this work. Comparing with the IQ receivers in Refs. [7, 8], although circuit functions are different, the on-chip 120 GHz VCO in this work reduces power consumption dramatically in comparison with ×16 multiplier chain for LO generation in Refs. [7, 8] and shows great advantage in power dissipation.

Parameter	RF (GHz)	ft/fmax (GHz)	Integration level	Conv. gain (dB)	Power dissipation (mW)	Input 1 dB CP (dBm)	NF (dB)	Bandwidth (GHz)
Ref. [1]	220	280/435	LNA, mixer	16	216	–	18	25
Refs. [3, 4]	245	300/500[19]	LNA, SHM, 120 GHz VCO, divider, LO-Buffer, on-chip antenna	18	712.3	?25	18	–
Ref. [7]	240	350/550	Balun, ×16 multiplier chain, mixer, PA, quadrature coupler, buffer, on-chip antenna	7.8	915.8	–	11.3	47
Ref. [8]	240	350/550	Balun, ×16 multiplier chain, mixer, PA,LNA, on-chip antenna	10.5	986	?18	15	17
Ref. [9]	240	300/500	TIA, LO multiplier (with external LO)	13	500	–	18	55
This work	245	300/500	CB LNA, 120 GHz VCO, divider, 2nd transconductance SHM, on-chip antenna	15	288/107 (with/without VCO and divider)	?24	17	15

Table2.
Comparison with state-of-the-art.



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Parameter	RF (GHz)	ft/fmax (GHz)	Integration level	Conv. gain (dB)	Power dissipation (mW)	Input 1 dB CP (dBm)	NF (dB)	Bandwidth (GHz)
Ref. [1]	220	280/435	LNA, mixer	16	216	–	18	25
Refs. [3, 4]	245	300/500[19]	LNA, SHM, 120 GHz VCO, divider, LO-Buffer, on-chip antenna	18	712.3	?25	18	–
Ref. [7]	240	350/550	Balun, ×16 multiplier chain, mixer, PA, quadrature coupler, buffer, on-chip antenna	7.8	915.8	–	11.3	47
Ref. [8]	240	350/550	Balun, ×16 multiplier chain, mixer, PA,LNA, on-chip antenna	10.5	986	?18	15	17
Ref. [9]	240	300/500	TIA, LO multiplier (with external LO)	13	500	–	18	55
This work	245	300/500	CB LNA, 120 GHz VCO, divider, 2nd transconductance SHM, on-chip antenna	15	288/107 (with/without VCO and divider)	?24	17	15

4.
Conclusion

A subharmonic receiver with low noise and high integration level for spectroscopy applications at 245 GHz consisting of a 245 GHz on-chip folded dipole antenna, a CB LNA, a 2nd transconductance SHM, and 120 GHz VCO with 1/64 frequency divider has been presented. Moreover, the used topology allowed a significant reduction of power consumption. The receiver reaches 15 dB gain at 245 GHz with bandwidth of 15 GHz in on-chip measurement with an external 245 GHz power source.

Acknowledgement

The authors are thankful for the IHP pilot line staff for excellent fabrication of the chip. The authors also thank Mr. Borngr?ber Johannes in IHP for measurement of the chip.