1.
Introduction
The ring oscillator finds various applications in the range of GHz, and voltage-controlled oscillators have been widely using it. The limitation of LC oscillators is the larger chip area, as they require spiral inductors; in addition, the tuning range of LC oscillators is relatively smaller[1, 2]. In comparison with the LC oscillator, the frequency of operation of the ring oscillator depends on the stage delay of CMOS inverter. In turn, the stage delay of inverter depends on the RC model of MOSFETs. Fig. 1 shows the general diagram of a 3-stage ring oscillator.
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Figure1.
Gate level diagram of 3-stage ring oscillator.
With the ring oscillator, for the completion of one cycle, the propagating signal has to pass twice through the stages. By making use of the stage delay (td) and the no. of stages (N), the frequency of operation is conventionally expressed as
$${f_{{ m{osc}}}} = frac{1}{{2N{t_{ m{d}}}}}.$$  | (1) |
For operating in the range of gigahertz, the ring oscillator does not require any external RC components, as the MOSFET itself provides the parasitic components. Thus, the stage delay is the same as the inverter delay[3]. In order to obtain the inverter delay, the gate capacitance of the inverter is utilized for the purpose of modeling. One method of computing the delay is in terms of the effective capacitance and the switching current[4, 5].
$${t_{ m{d}}} = frac{{{C_{{ m{total}}}}{V_{{ m{dd}}}}}}{{{I_{ m{D}}}}}.$$  | (2) |
This model includes the Miller capacitance effect, and hence is useful for the designer[6, 7]. But the limitation is that, with reference to the switching transition, this model yields the total capacitance, Ctot = 2.5(COXp + COXn), and the current or resistance calculations have to be performed by the designer alone[8, 9]. In addition, the submicron parasitic effects are ignored in this model, as it is primarily meant for the micrometer dimensions.
In this paper, an effort has been made to overcome the limitations mentioned above. The paper is organized as follows. Section 2 considers the parasitic switching effects, and deals with the RC switching model of the ring oscillator. In Section 3, the derivation of an equation for the oscillating frequency is discussed, based on the model proposed in the previous section. In Section 4, the circuit simulation results and the verification of the derived equation are elaborated. Finally, Section 5 concludes the results obtained.
2.
Switching model in terms of RC
In the BSIM 4V4.8.0 SPICE model, for each type of MOSFET, there are more than 200 parameters. Hence for the manual calculations, it is not possible for the circuit designer, to make use of these many parameters. The primary purpose of these parameters is to aid in the characterization of devices for the purpose of simulation[10, 11]. Hence, during the design of CMOS ring oscillators in the submicron technology nodes, it is preferable to use the design equations of the first order, keeping the second order effects in mind. An effort is made in this work, to arrive at an equation for the oscillating frequency of the ring oscillator, in terms of the dimensions of the device. The modeling of the switching transistors is performed after considering the submicron switching behavior of the devices. The circuit diagram is shown in Fig. 2 for a 3-stage ring oscillator, and Fig. 3 shows the RC model.
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Figure2.
Circuit diagram of 3-stage CMOS ring oscillator.
The initial input to PM1 and NM1 is considered as “0”, and the RC model is constructed as shown in Fig. 3. The channel resistances for p and n type MOSFETs are represented as RSDp and RDSn, and the gate capacitances for the same are represented as CGp and CGn. In addition, the drain capacitances with respect to the body are shown as CDBp and CDBn. These parasitic capacitances are also called junction capacitances or diffusion capacitances. As the NMOS source is connected to ground and PMOS source is connected to VDD, the parasitic source capacitances with respect to the body or substrate are ignored.
3.
Expression for the frequency
For the purpose of arriving at the frequency of operation, the stage delay can be modeled in terms of the transitions at the output, i.e., low-to-high and high-to-low. As the output of the ring oscillator does not contain any steady logic state of ‘0’ or ‘1’, the stage delay can be expressed using the time constants, τPLH and τPHL. Thus,
$${t_{ m{d}}} = {tau _{{ m{pLH}}}} + {tau _{{ m{pHL}}}}.$$  | (3) |
Hence, Eq. (1) gets modified as,
$${f_{{ m{osc}}}} = frac{1}{{2Nleft( {{tau _{{ m{pLH}}}} + {tau _{{ m{pHL}}}}} ight)}}.$$  | (4) |
The first order equations for the transistors are chiefly utilized for micrometer dimensions, and they are not accurate in the nanometer dimensions. But, as the BSIM 4V4.8.0 SPICE model contains more than 200 parameters, it is extremely difficult to consider all the second order effects, in arriving at the design equation for the output frequency of ring oscillator, in terms of its RC delay. Therefore, the modeling can be performed by utilizing the first order design equations of the MOSFETs. From the RC switching model of the ring oscillator shown in Fig. 3, the intrinsic delays can be written as,
$${tau _{{ m{pLH}}}} = 0.7{R_{{ m{SDp}}1}}{C_{{ m{tot}}1}},$$  | (5) |
$${tau _{{ m{pHL}}}} = 0.7{R_{{ m{DSn}}2}}{C_{{ m{tot}}2}},$$  | (6) |
where Ctot1 is the capacitance when the inverter’s output is at logic ‘1’, and Ctot2 is the capacitance when the output is at logic ‘0’. The capacitances Ctot1 and Ctot2 can be computed by utilizing Fig. 3. The resistances and the capacitances can be computed for the two cases of output, by individually computing the R and C with respect to the individual nodes.
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Figure3.
RC model of 3-stage CMOS ring oscillator.
During the switching of an inverter, there are five regions of operation in the DC characteristics. For the practical purposes of the ring oscillator functionality, when p-MOSFET is in cutoff region, N-MOSFET is in linear region, and vice versa, during 50% of the time. During the remaining 50% of the time, both MOSFETs are operating in saturation region[12]. Therefore, for obtaining the time constants in terms of R and C, it becomes necessary to compute their values for both of these cases.
3.1
When one MOSFET is in linear region and the other is in cutoff
Irrespective of the switching conditions of the MOSFETs, the drain-to-body capacitance is present as parasitic junction capacitance with both of them. Hence, when NM1 is in the cutoff region, Ctot1 is expressed as,
$${C_{{ m{tot}}1}} = {C_{{ m{Gp}}2}} + {C_{{ m{Gn}}2}} + {C_{{ m{DBp}}1}} + {C_{{ m{DBn}}1}},$$  | (7) |
$${C_{{ m{tot}}2}} = {C_{{ m{Gp}}3}} + {C_{{ m{Gn}}3}} + {C_{{ m{DBp}}2}} + {C_{{ m{DBn}}2}},$$  | (8) |
The gate capacitance is given by,
$${C_{ m{G}}} = {C_{{ m{GC}}}} + {C_{{ m{GD}}}} + {C_{{ m{GS}}}},$$  | (9) |
where CGC is gate-to-channel capacitance, CGD is gate-to-drain capacitance, and CGS is gate-to-source capacitance. The junction or diffusion capacitance CDB is decomposed into two components namely bottom plate capacitance and sidewall capacitance, specified per unit area and unit length respectively. The first component gets multiplied by the drain area and the second component gets multiplied by the drain perimeter[13].
It is deduced from the results of the submicron characterization, that when the MOSFET is operating in cutoff region, the values of CGD and CGS are negligible. But when the MOSFET is operating in linear region, they have the value that is half of CGC. Further, even though the value of diffusion capacitance depends on both area and perimeter, the effective capacitance averaged over the switching range is quite satisfactory for digital applications. Hence, for the purpose of manual performance estimation, it is observed that the value of CDB is comparable to CGC[14].
Therefore, from Eq. (9), when PM2 is in cutoff region and when NM2 is in linear region,
$${C_{{ m{Gp}}2}} = C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}},$$  | (10) |
$${C_{{ m{Gn}}2}} = C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}} + frac{1}{2}C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}} + frac{1}{2}C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}}.$$  | (11) |
Therefore, substituting Eqs. (10) and (11) in Eq. (7), and then substituting for the diffusion capacitances as
m{DBp}}}} = C_{{
m{ox}}}'{W_{
m{p}}}{L_{
m{p}}}$
m{DBn}}}} = C_{{
m{ox}}}'{W_{
m{n}}}{L_{
m{n}}}$
$${C_{{ m{tot}}1}} = C_{{ m{ox}}}'(2{W_{ m{p}}}{L_{ m{p}}} + 3{W_{ m{n}}}{L_{ m{n}}}).$$  | (12) |
Similarly, when PM3 is in linear region and when NM3 is in cutoff region,
$${C_{{ m{Gp}}3}} = C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}} + frac{1}{2}C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}} + frac{1}{2}C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}},$$  | (13) |
$${C_{{ m{Gn}}3}} = C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}}.$$  | (14) |
Therefore, substituting Eqs. (13) and (14) in Eq. (8), and then substituting for CDBp and CDBn,
$${C_{{ m{tot}}2}} = C_{{ m{ox}}}'(3{W_{ m{p}}}{L_{ m{p}}} + 2{W_{ m{n}}}{L_{ m{n}}}).$$  | (15) |
Now, to proceed with the computation of channel resistance, in the expression for IDS in the linear region, the second term (VDS2/2) can be ignored, as its value is very small. In addition, with digital switching circuits, the channel length modulation factor can be ignored, as the effect of VDS on the switching is very small[15]. Hence,
$${R_{{ m{SDp}}left( {{ m{linear}}} ight)}} = frac{{{L_{ m{p}}}}}{{{mu _{ m{p}}}C_{{ m{ox}}}'{W_{ m{p}}}left( {{V_{{ m{SGp}}}} - left| {{V_{{ m{tp}}}}} ight|} ight)}},$$  | (16) |
$${R_{{ m{DSn}}left( {{ m{linear}}} ight)}} = frac{{{L_{ m{n}}}}}{{{mu _{ m{n}}}C_{{ m{ox}}}'{W_{ m{n}}}({V_{{ m{GSn}}}} - {V_{{ m{tn}}}})}}.$$  | (17) |
Therefore, substituting Eqs. (12) and (16) in Eq. (5), and Eqs. (15) and (17) in Eq. (6),
$${tau _{{ m{pLH}}}} = 0.7frac{{{L_{ m{p}}}}}{{{mu _{ m{p}}}C_{{ m{ox}}}'{W_{ m{p}}}left( {{V_{{ m{SGp}}}} - left| {{V_{{ m{tp}}}}} ight|} ight)}}C_{{ m{ox}}}'left( {2{W_{ m{p}}}{L_{ m{p}}} + 3{W_{ m{n}}}{L_{ m{n}}}} ight),$$  | (18) |
$${tau _{{ m{pHL}}}} = 0.7frac{{{L_{ m{n}}}}}{{{mu _{ m{n}}}C_{{ m{ox}}}'{W_{ m{n}}}({V_{{ m{GSn}}}} - {V_{{ m{tn}}}})}}C_{{ m{ox}}}'left( {3{W_{ m{p}}}{L_{ m{p}}} + 2{W_{ m{n}}}{L_{ m{n}}}} ight).$$  | (19) |
When all p-devices have the same width, and all n-devices also have the same width, Wp/Wn is called Beta ratio[16]. However, for all the devices, the channel lengths are chosen as the same value; i.e., Lp = Ln = L. For TSMC 180 nm process, the values of SPICE parameters are, μn = 2.6365 × 10?2 m2/(V·s), μp = 1.1498 × 10?2 m2/(V·s), Vtn = 0.372 V and Vtp = ?0.387 V. Substituting these values in Eqs. (18) and (19) and choosing VDD = 1.8 V,
$${tau _{{ m{pLH}}}} = 43.09{L^2}left( {2 + 3frac{{{W_{ m{n}}}}}{{{W_{ m{p}}}}}} ight),$$  | (20) |
$${tau _{{ m{pHL}}}} = 18.59{L^2}left( {2 + 3frac{{{W_{ m{p}}}}}{{{W_{ m{n}}}}}} ight).$$  | (21) |
3.2
When both MOSFETs are switching in the saturation region
When the submicron MOSFET is operating in saturation region, CGD can be ignored due to pinch-off, and CGS has the value that is 2/3rd of CGC[14]. Hence, using Eq. (9),
$${C_{{ m{Gp}}2}} = C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}} + frac{2}{3}C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}},$$  | (22) |
$${C_{{ m{Gn}}2}} = C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}} + frac{2}{3}C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}}.$$  | (23) |
Therefore, substituting Eqs. (22) and (23) in Eq. (7), and substituting for CDB,
$${C_{{ m{tot}}1}} = frac{8}{3}C_{{ m{ox}}}'({W_{ m{p}}}{L_{ m{p}}} + {W_{ m{n}}}{L_{ m{n}}}).$$  | (24) |
Similarly, when PM3 and NM3 are in saturation region,
$${C_{{ m{Gp}}3}} = C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}} + frac{2}{3}C_{{ m{ox}}}'{W_{ m{p}}}{L_{ m{p}}},$$  | (25) |
$${C_{{ m{Gn}}3}} = C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}} + frac{2}{3}C_{{ m{ox}}}'{W_{ m{n}}}{L_{ m{n}}}.$$  | (26) |
Therefore, substituting Eqs. (25) and (26) in Eq. (8), and substituting for CDB,
$${C_{{ m{tot}}2}} = frac{8}{3}C_{{ m{ox}}}'({W_{ m{p}}}{L_{ m{p}}} + {W_{ m{n}}}{L_{ m{n}}}).$$  | (27) |
In the saturation region, VDS = VGS ? Vt. Thus, the channel resistances can be expressed as,
$${R_{{ m{SDp}}left( {{ m{saturation}}} ight)}} = frac{{2{L_{ m{p}}}}}{{{mu _{ m{p}}}C_{{ m{ox}}}'{W_{ m{p}}}left( {{V_{{ m{SGp}}}} - left| {{V_{{ m{tp}}}}} ight|} ight)}},$$  | (28) |
$${R_{{ m{DSn}}left( {{ m{saturation}}} ight)}} = frac{{2{L_{ m{n}}}}}{{{mu _{ m{n}}}C_{{ m{ox}}}'{W_{ m{n}}}({V_{{ m{GSn}}}} - {V_{{ m{tn}}}})}}.$$  | (29) |
Therefore, substituting Eqs. (24) and (28) in Eq. (5), and Eqs. (27) and (29) in Eq. (6), we obtain,
$${tau _{{ m{pLH}}}} = 0.7frac{{2{L_{ m{p}}}}}{{{mu _{ m{p}}}C_{{ m{ox}}}'{W_{ m{p}}}left( {{V_{{ m{SGp}}}} - left| {{V_{{ m{tp}}}}} ight|} ight)}}frac{8}{3}C_{{ m{ox}}}'left( {{W_{ m{p}}}{L_{ m{p}}} + {W_{ m{n}}}{L_{ m{n}}}} ight),$$  | (30) |
$${tau _{{ m{pHL}}}} = 0.7frac{{2{L_{ m{n}}}}}{{{mu _{ m{n}}}C_{{ m{ox}}}'{W_{ m{n}}}({V_{{ m{GSn}}}} - {V_{{ m{tn}}}})}}frac{8}{3}C_{{ m{ox}}}'left( {{W_{ m{p}}}{L_{ m{p}}} + {W_{ m{n}}}{L_{ m{n}}}} ight).$$  | (31) |
Substituting the values of μn, μp, Vtn and Vtp in Eqs. (30) and (31),
$${tau _{{ m{pLH}}}} = 229.79{L^2}left( {1 + frac{{{W_{ m{n}}}}}{{{W_{ m{p}}}}}} ight),$$  | (32) |
$${tau _{{ m{pHL}}}} = 99.16{L^2}left( {1 + frac{{{W_{ m{p}}}}}{{{W_{ m{n}}}}}} ight).$$  | (33) |
Denoting Wp/Wn = B, substituting Eqs. (20), (21), (32) and (33) in Eq. (3),
$$begin{split} {t_{text{d}}} =,, & {L^2}left[ {43.09left( {2 + frac{3}{B}} ight) + 18.59left( {2 + 3B} ight)} ight. hfill & left. { +,, 229.79left( {1 + frac{1}{B}} ight) + 99.16left( {1 + B} ight)} ight]. hfillend{split}$$  | (34) |
Finally, in accordance with Eq. (4), the time period of N-stage ring oscillator is,
$$begin{split} {tau _{{text{osc}}}} = ,, & 2N{L^2}left[ {43.09left( {2 + frac{3}{B}} ight) + 18.59left( {2 + 3B} ight)} ight. hfill & left. { +,, 229.79left( {1 + frac{1}{B}} ight) + 99.16left( {1 + B} ight)} ight]. hfill end{split} $$  | (35) |
The simplified version of Eq. (35) is,
$${tau _{{ m{osc}}}} = 2N{L^2}left[ {452.31 + frac{{359.06{W_{ m{n}}}}}{{{W_{ m{p}}}}} + frac{{154.93{W_{ m{p}}}}}{{{W_{ m{n}}}}}} ight].$$  | (36) |
In TSMC 180 nm process, the electron mobility is 2.3 times larger than hole mobility[17]. Therefore, for the channel resistances to be equilibrated, and for the inverters to switch at the mid-point of VDD, Wp has to be by 2.3 times more than Wn. Hence when B = 2.3, for the N-stage ring oscillator, the frequency of oscillations is obtained from Eq. (36) as,
$${f_{{ m{osc}}}} = frac{1}{{1929.52N{L^2}}}.$$  | (37) |
From Eq. (36), it is seen that the frequency of oscillations is inversely proportional to the square of the channel length, and also to the number of stages. It can also be observed from Eq. (37) that, when the beta ratio is kept fixed, the value of the frequency does not depend on the width of the MOSFETs.
4.
Circuit simulation and results
To verify the equation that got derived, simulation of the ring oscillator’s circuit is performed in TSMC 180 nm, utilizing Cadence Virtuoso. The earlier work of the authors on the characterization of ring oscillator was performed by keeping the beta ratio fixed at 2.3[18, 19]. In this particular work, the design is extended to encompass the asymmetric MOSFET dimensions, so as to have a width-independent approach. The width of N-MOSFET is chosen from 0.8 to 2.4 μm, with the Beta ratio chosen as 1, 2, 2.3 and 3. Fig. 4 shows the circuit diagram of a 5-stage CMOS ring oscillator, and Fig. 5 shows the simulation result.
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Figure4.
5-stage ring oscillator’s schematic diagram.
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Figure5.
5-stage ring oscillator’s output waveform.
To reduce the startup time, a weak P-device is used as a keeper, to inject a small amount of current to the very first inverter. However, as this device width is chosen as only 0.4 μm, it lacks drive strength, and thus, does not affect the operation of the oscillator. The circuit simulations were further performed in 2 steps: (i) with 4 different values of Beta ratio, for 5 different widths of N-MOSFET, (ii) with 10 different values of ring oscillator stage, starting from 5 to 23. The results are tabulated in Tables 1 & 2 respectively, the frequencies being in GHz. From Table 1, it is seen that the computed value and the simulated value have a slight difference. This difference is due to the overlapping capacitance, which was ignored during the analysis. However, the overlap is important in the structure of the MOSFET, in order to maintain the continuity of the channel, so as to overcome the effect of process variations. Further, it is observed that, when Wn = Wp, the deviation is on the negative side, which indicates that such Beta ratio is not permissible. This is evident from the mobility difference in between the electrons and holes.
| Sl. no. | Wn (μm) | B | Wp (μm) | Beta ratio (normalized) | fosc (GHz) (computed) | fosc (GHz) (simulated) | Deviation (%) |
| 01 | 0.80 | 1.0 | 0.80 | 1.00 | 3.1941 | 3.2776 | ?2.61 |
| 02 | 0.80 | 2.0 | 1.60 | 1.10 | 3.2775 | 3.1979 | 2.43 |
| 03 | 0.80 | 2.3 | 1.84 | 1.13 | 3.1991 | 3.1240 | 2.35 |
| 04 | 0.80 | 3.0 | 2.40 | 1.20 | 2.9768 | 2.9360 | 1.37 |
| 05 | 1.20 | 1.0 | 1.20 | 1.50 | 3.1941 | 3.2541 | ?1.88 |
| 06 | 1.20 | 2.0 | 2.40 | 1.60 | 3.2775 | 3.1746 | 3.14 |
| 07 | 1.20 | 2.3 | 2.76 | 1.63 | 3.1991 | 3.1008 | 3.07 |
| 08 | 1.20 | 3.0 | 3.60 | 1.70 | 2.9768 | 2.9129 | 2.15 |
| 09 | 1.60 | 1.0 | 1.60 | 2.00 | 3.1941 | 3.2404 | ?1.45 |
| 10 | 1.60 | 2.0 | 3.20 | 2.10 | 3.2775 | 3.1646 | 3.44 |
| 11 | 1.60 | 2.3 | 3.68 | 2.13 | 3.1991 | 3.0902 | 3.40 |
| 12 | 1.60 | 3.0 | 4.80 | 2.20 | 2.9768 | 2.8918 | 2.86 |
| 13 | 2.00 | 1.0 | 2.00 | 2.50 | 3.1941 | 3.2300 | ?1.12 |
| 14 | 2.00 | 2.0 | 4.00 | 2.60 | 3.2775 | 3.1576 | 3.66 |
| 15 | 2.00 | 2.3 | 4.60 | 2.63 | 3.1991 | 3.0817 | 3.67 |
| 16 | 2.00 | 3.0 | 6.00 | 2.70 | 2.9768 | 2.8852 | 3.08 |
| 17 | 2.40 | 1.0 | 2.40 | 3.00 | 3.1941 | 3.2185 | ?0.76 |
| 18 | 2.40 | 2.0 | 4.80 | 3.10 | 3.2775 | 3.1526 | 3.81 |
| 19 | 2.40 | 2.3 | 5.52 | 3.13 | 3.1991 | 3.0722 | 3.97 |
| 20 | 2.40 | 3.0 | 7.20 | 3.20 | 2.9768 | 2.8835 | 3.13 |
Table1.
Frequency values with variation in B (with N = 5).
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| Sl. no. | Wn (μm) | B | Wp (μm) | Beta ratio (normalized) | fosc (GHz) (computed) | fosc (GHz) (simulated) | Deviation (%) |
| 01 | 0.80 | 1.0 | 0.80 | 1.00 | 3.1941 | 3.2776 | ?2.61 |
| 02 | 0.80 | 2.0 | 1.60 | 1.10 | 3.2775 | 3.1979 | 2.43 |
| 03 | 0.80 | 2.3 | 1.84 | 1.13 | 3.1991 | 3.1240 | 2.35 |
| 04 | 0.80 | 3.0 | 2.40 | 1.20 | 2.9768 | 2.9360 | 1.37 |
| 05 | 1.20 | 1.0 | 1.20 | 1.50 | 3.1941 | 3.2541 | ?1.88 |
| 06 | 1.20 | 2.0 | 2.40 | 1.60 | 3.2775 | 3.1746 | 3.14 |
| 07 | 1.20 | 2.3 | 2.76 | 1.63 | 3.1991 | 3.1008 | 3.07 |
| 08 | 1.20 | 3.0 | 3.60 | 1.70 | 2.9768 | 2.9129 | 2.15 |
| 09 | 1.60 | 1.0 | 1.60 | 2.00 | 3.1941 | 3.2404 | ?1.45 |
| 10 | 1.60 | 2.0 | 3.20 | 2.10 | 3.2775 | 3.1646 | 3.44 |
| 11 | 1.60 | 2.3 | 3.68 | 2.13 | 3.1991 | 3.0902 | 3.40 |
| 12 | 1.60 | 3.0 | 4.80 | 2.20 | 2.9768 | 2.8918 | 2.86 |
| 13 | 2.00 | 1.0 | 2.00 | 2.50 | 3.1941 | 3.2300 | ?1.12 |
| 14 | 2.00 | 2.0 | 4.00 | 2.60 | 3.2775 | 3.1576 | 3.66 |
| 15 | 2.00 | 2.3 | 4.60 | 2.63 | 3.1991 | 3.0817 | 3.67 |
| 16 | 2.00 | 3.0 | 6.00 | 2.70 | 2.9768 | 2.8852 | 3.08 |
| 17 | 2.40 | 1.0 | 2.40 | 3.00 | 3.1941 | 3.2185 | ?0.76 |
| 18 | 2.40 | 2.0 | 4.80 | 3.10 | 3.2775 | 3.1526 | 3.81 |
| 19 | 2.40 | 2.3 | 5.52 | 3.13 | 3.1991 | 3.0722 | 3.97 |
| 20 | 2.40 | 3.0 | 7.20 | 3.20 | 2.9768 | 2.8835 | 3.13 |
| Sl. no. | N | fosc (GHz) (computed) | fosc (GHz) (simulated) | Deviation (%) | ||
| 01 | 05 | 3.1991 | 3.0817 | 3.67 | ||
| 02 | 07 | 2.2851 | 2.1993 | 3.76 | ||
| 03 | 09 | 1.7773 | 1.7123 | 3.66 | ||
| 04 | 11 | 1.4541 | 1.4008 | 3.67 | ||
| 05 | 13 | 1.2304 | 1.1861 | 3.60 | ||
| 06 | 15 | 1.0664 | 1.0274 | 3.65 | ||
| 07 | 17 | 0.9409 | 0.9071 | 3.59 | ||
| 08 | 19 | 0.8419 | 0.8114 | 3.62 | ||
| 09 | 21 | 0.7617 | 0.7341 | 3.62 | ||
| 10 | 23 | 0.6955 | 0.6705 | 3.60 |
Table2.
Frequency values with variation in N (with Wn = 2 μm, B = 2.3).
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| Sl. no. | N | fosc (GHz) (computed) | fosc (GHz) (simulated) | Deviation (%) | ||
| 01 | 05 | 3.1991 | 3.0817 | 3.67 | ||
| 02 | 07 | 2.2851 | 2.1993 | 3.76 | ||
| 03 | 09 | 1.7773 | 1.7123 | 3.66 | ||
| 04 | 11 | 1.4541 | 1.4008 | 3.67 | ||
| 05 | 13 | 1.2304 | 1.1861 | 3.60 | ||
| 06 | 15 | 1.0664 | 1.0274 | 3.65 | ||
| 07 | 17 | 0.9409 | 0.9071 | 3.59 | ||
| 08 | 19 | 0.8419 | 0.8114 | 3.62 | ||
| 09 | 21 | 0.7617 | 0.7341 | 3.62 | ||
| 10 | 23 | 0.6955 | 0.6705 | 3.60 |
Later on, from Table 2, it is seen that, from 5-stage to 23-stage, when B = 2.3, the difference percentage remains almost the same. During simulation, it was observed that the difference does not vary much for other values of B. Therefore, to have optimum drive strength, the widths are chosen as, Wn = 2 μm, and Wp = 4.6 μm, according to the Beta ratio prescribed for TSMC 180 nm technology. The results tabulated in Tables 1 and 2 are plotted in Figs. 6 and 7 respectively. The minimum value of Wn is chosen as 800 nm, and the next widths are selected in its multiples, till 2400 nm. For the purpose of plotting the frequency with respect to asymmetric widths, the Beta ratio is normalized using the minimum width chosen, i.e., 800 nm, with Wp–Wn. With the observation of the results tabulated in Table 2, a correction factor, which corresponds to the average 3.64% difference, can be introduced into Eq. (37), so as to obtain a value that is nearer to the simulated value. Therefore, the final empirical expression for the operating frequency when B = 2.3 is,
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Figure6.
(Color online) Beta ratio versus frequency of 5-stage ring oscillator.
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Figure7.
(Color online) Plot of computed versus simulated frequencies for different stages.
$${f_{{ m{osc}}}} = frac{1}{{2000N{L^2}}}.$$  | (38) |
5.
Conclusion
Modeling of the ring oscillator is presented in terms of the device switching behavior. Using this model, a new formula is derived for the frequency of oscillations. The formula contains only three terms: the number of stages, the device length, and an empirical constant. This formula helps the designer for the hand calculations, thus avoiding the large number of circuit simulations. During simulations with the 180 nm library, the influence of the short channel effects is found to be 3.64%, on an average. For the other technology nodes, the amount of influence can be found with one simulation experiment, by using the respective library, and an empirical constant can be arrived at. Finally, it can be concluded that, for any nanometer node, τosc is directly proportional to the term NL2. Therefore, the new formula can be utilized for arriving at faster results while designing the CMOS ring oscillator in the GHz range.
This particular work is focused on a single-ended ring oscillator circuit. But differential topology ring oscillators have better noise performance when compared to the single-ended ones. Therefore, as a future enhancement, a similar modeling approach can be implemented on the circuit of a differential ring oscillator, to obtain a formula for its frequency of operation.
