康婧^{1, 2,,},
安军社¹,
王冰冰^{1, 2}
1.中国科学院国家空间科学中心 北京 100190
2.中国科学院大学 北京 100049
基金项目:中国科学院空间科学先导卫星专项(XDA15320100)

详细信息

作者简介:康婧：女，1993年生，博士生，研究方向为数字通信、信道编译码技术及大规模集成电路设计
安军社：男，1969年生，研究员，研究方向为空间综合电子技术
王冰冰：男，1996年生，硕士生，研究方向为信道编译码技术

通讯作者:康婧　k_naive@163.com

中图分类号:TN911.22

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被引次数:0

出版历程

收稿日期:2020-02-21
修回日期:2021-06-07
网络出版日期:2021-07-12
刊出日期:2021-12-21

Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions

Jing KANG^{1, 2,,},
Junshe AN¹,
Bingbing WANG^{1, 2}
1. National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China
2. University of Chinese Academy of Sciences, Beijing 100049, China
Funds:The Space Science Leading Satellite Project, Chinese Academy of Sciences(XDA15320100)


摘要
摘要:为满足近地轨道(LEO)卫星星地高速数传系统对高通量、低复杂度、高可靠性信道编码的应用需求，该文提出一种基于国际空间数据系统咨询委员会(CCSDS)近地卫星通信标准低密度奇偶校验(LDPC)码的低复杂度可重构编码器设计实现方案。通过对输入信息比特插0处理和拆分循环矩阵，并分析不同并行度编码的结构特点，实现了可重构编码方案，提高了编码器的灵活性和编码数据吞吐率；采用优化的移位寄存器累加单元，降低了编码器的整体硬件资源规模。在Xilinx FPGA上对提出的编码器进行了实现，结果表明，在125 MHz系统工作时钟下，编码数据吞吐率最高可达1 Gbps，归一化编码数据吞吐率与其它文献并行度相近的编码器相比提高了17.1%，其寄存器资源和查找表资源与相同平台已有方案相比分别降低了13.7%和14.8%。
关键词:星地高速数传/
低密度奇偶校验码/
可重构/
低复杂度/
FPGA
Abstract:A new low complexity and reconfigurable Low Density Parity Check (LDPC) encoder design based on the Consultative Committee for Space Data Systems (CCSDS) standard is proposed to meet the high throughput, low latency and high reliability requirement for high-speed satellite-to-ground data transmission systems of Low Earth Orbit (LEO). This design is parallel reconfigurable by inserting 0 into information bits and splitting cyclic matrices, and analyzed the structural characteristics of different parallelism encoding. Benefitting from the parallel reconfiguration, the throughput is increased and the flexibility is guaranteed. Furthermore, using optimized shift register adder accumulators can reduce the hardware resources. The proposed encoder design is implemented on Xilinx FPGA. The experimental results show that the maximum encoding speed is up to 1 Gbps @125 MHz, and the normalized throughput is increased by 17.1% compared with the similar parallel encoder. And resources of registers and look-up tables are reduced by 13.7% and 14.8% respectively, compared with the existing encoder.
Key words:High-speed satellite-to-ground data transmissions/
Low Density Parity Check (LDPC)/
Reconfigurable/
Low complexity/
FPGA



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