导师介绍
姓名 李华伟 性别 女
联系方式 lihuawei@ict.ac.cn 职称 研究员
研究方向 数字集成电路测试、验证、可靠性设计、容错计算
个人介绍
简历:
李华伟，女，博士，IEEE Senior Member。2008年获中国科学院（下称中科院）卢嘉锡青年人才奖，2012年入选中科院青年创新促进会成员；2012年荣获国家技术发明二等奖，2014年荣获北京市科学技术奖一等奖。
现任中科院计算技术研究所（下称计算所）研究员，博士生导师，计算机体系结构国家重点实验室-VLSI测试与验证组组长，中国计算机学会-容错计算专业委员会秘书长。《IEEE Transaction on VLSI Systems》Associate Editor，《计算机辅助设计与图形学学报》、《计算机研究与发展》编委。IEEE寄存器传输级与高层测试研讨会指导委员会主席；IEEE亚洲测试学术会议指导委员会成员。
主要从事数字集成电路测试、验证与可靠性技术研究，先后主持和参加了近二十项国家自然科学基金(NSFC)、973、863等科研项目的研究工作。发表学术论文130余篇，其中IEEE/ACM期刊18篇，SCI索引30篇，EI索引120余篇；授权发明专利20项。
最新更新参见国科大教师主页：http://people.ucas.ac.cn/~lihuawei


研究方向:
数字集成电路测试、验证、可靠性设计、容错计算
社会任职:
[1] 中国计算机学会（简称CCF），容错计算专业委员会，秘书长(2008-)
[2] IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 编委(2015-)
[3] IEEE Asian Test Symposium (ATS)的Steering Committee成员 (2013-)
[4] IEEE Workshop on RTL & High-Level Testing (WRTLT)的Steering Committee主席 (2014-)
[5] 《计算机辅助设计与图形学学报》编委 (2010-)
[6] 《计算机研究与发展》编委 (2014-)
[7] General Co-Chair, 23rd IEEE ATS, Hangzhou, 2014
[8] Topic Coordinator in Program Committee, 43rd and 44th IEEE International Test Conference (ITC, Anaheim, USA, 2012/2013)
[9] TPC Subcommittee Chair for Track “Test and DFT”, 18th IEEE Asia and South Pacific Design Automation Conference (ASP-DAC, Yokohama, Japan, 2013)
[10] Program Co-Chair, 16th IEEE ATS, Beijing, 2007
[11] Program Chair, 4th IEEE WRTLT, Xi’an, 2003
[12] 程序（合作）主席，CCF第四届/第三届中国测试学术会议，秦皇岛/长沙，2006/2004年

获奖及荣誉:
[1] 2012年度国家技术发明奖二等奖，获奖项目：“星载微处理器系统验证-测试-恢复技术及应用”
[2] 2014年度北京市科学技术奖一等奖，获奖项目：“32位星载容错控制计算机系统关键技术及应用”
[3] 2011年度中国质量协会质量技术奖一等奖，获奖项目：“高性能处理芯片的测试和可靠性设计关键技术”
[4] 2008年度中国科学院卢嘉锡青年人才奖，2012年入选中国科学院青年创新促进会成员
[5] 2008年度中国计算机学会王选奖二等奖，获奖项目：“数字电路测试若干关键技术及其在微处理器测试中的应用”
[6] 2008年度北京市科学技术奖（发明类）三等奖，获奖项目：“数字电路实速检测和故障诊断技术及其应用”
[7] 2007年度北京市科学技术奖（基础研究类）三等奖，获奖项目：“集成电路逻辑测试与验证基础技术”
[8] 2003年度中国科学院杰出科技成就奖，获奖团队：“龙芯CPU”研究集体
[9] 2004年度全国优秀博士论文提名：“基于RTL行为模型的测试产生及时延测试方法”
[10] 2001年度中国科学院院长奖学金特别奖

代表论著:
[1]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.
[2]Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.
[3]Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.
[4]Shuangde Fang, Zidong Du, Yuntan Fang, Yuanjie Huang, Yang Chen, Lieven Eeckhout, Olivier Temam, Huawei Li, Yunji Chen, Chengyong Wu, “Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach,” ACM Transactions on Architecture and Code Optimization (TACO), Vol. 11, No. 2, Article 21, June 2014.
[5]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.
[6]Ying Wang, Lei Zhang, Yinhe Han and Huawei Li, “Reinventing Memory System Design for Many-Accelerators Architecture”, Journal of Computing Science and Technology (JCST), Vol.29, No.2, Feb. 2014, pp.273-280.
[7]Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.
[8]Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.
[9] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.
[10] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247.
[11] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.
[12] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.
[13] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.
[14] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.
[15] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “RADAR: A Case for Retention-Aware DRAM Assembly and Repair in Future FGR DRAM Memory”, to appear in IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2015.
[16] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Processing”, to appear in IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2015.
[17] Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu, “Retraining based Timing Error Mitigation for Hardware Neural Networks,” Proc. Design Automation and Test in Europe (DATE) , pp.593-596, France, March 2015.
[18] Yun Cheng, Huawei Li, Xiaowei Li, “An On-Line Timing Error Detection Method for Silicon Debug,” Proc. of 23rd IEEE ATS, pp.263-268, Nov. 2014.
[19] Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li, “HARS: A High-Performance Reliable Routing Scheme for 3D NoCs,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 392-397, July 2014.
[20] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, and Xiaowei Li, “Functional Test Generation Guided by Steady-State Probabilities of Abstract Design,” Proc. Design Automation and Test in Europe (DATE) , Paper IP5-13, March 2014.
[21] Jian Wang, Huawei Li, Xiaowei Li, “A novel abstraction-guided simulation approach using posterior probabilities for verification,” Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT’) , Paper DR111, April 2014.
[22] Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li, “Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube,” Proc. of 33rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.295-300, San Jose, Nov. 2014.
[23] Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li, “Path Constraint Solving based Test Generation for Hard-to-reach States,” IEEE Asian Test Symposium (ATS’13), Taiwan, 2013, pp.239-244.
[24] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc.of IEEE VLSI TestSymposium (VTS’13), Berkeley, CA, USA, May 2013.
[25] Yuntan Fang, Huawei Li, Xiaowei Li, “SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write,” Proc.of IEEE Asian TestSymposium (ATS’12), Niigata, Japan, Nov. 2012, pp.131-136.
[26] Xuefeng Zhu, Huawei Li, Xiaowei Li, “Statistical SDFC:A Metric for Evaluating Test Quality of Small Delay Faults,” Proc. 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), paper T6.3, Hsinchu, Taiwan, April 2012. (EI)
[27] Yuntan Fang, Huawei Li, Xiaowei Li, “A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications,” Proc.of IEEE Asian TestSymposium (ATS’11), New Delhi, India, Nov. 2011, pp.329-334.
[28] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), invited paper in Special Session I (GPU Applications), Hsinchu, Taiwan, April 2011.
[29] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, and Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing,” Proc. of International Symposium on Computer Architecture (ISCA’11), 2011, pp.259-270.
[30] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", Proc. IEEE VLSI Test Symposium (VTS’11), 2011, pp.272-277.
[31] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Flex memory: Exploiting and managing abundant off-chip optical bandwidth,” Proc. Design Automation and Test in Europe (DATE’11), pp. 968-973.
[32] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” Proc. IEEE 41st International Test Conference (ITC’10), Paper 12.1, Austin, USA, Oct. 2010.

承担科研项目情况:
1. 国家自然科学基金重点项目：差错容忍计算器件基础理论与方法
2. 国家自然科学基金面上项目：考虑集成电路时延变异性的硅后定时验证方法。
3. 国家973课题：高性能处理芯片的设计验证与测试。
4. 国家自然科学基金面上项目：避免过度测试的时延测试方法。
5. 国家自然科学基金面上项目：面向串扰的时延测试。
6. 国家863项目：可信计算平台软硬件系统安全测试评估模型、测试方法以及测试自动化技术。

学科类别:
计算机系统结构
所属部门:
计算机体系结构国家重点实验室
专家类别:
正高
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