基本信息
李华伟女博导中国科学院计算技术研究所
电子邮件： lihuawei@ict.ac.cn
通信地址： 海淀区科学院南路6号中科院计算所体系结构国家重点实验室
邮政编码： 100190

研究领域
集成电路设计自动化、智能计算、近似计算、容错计算、设计验证与测试



招生信息

招生方向：集成电路设计自动化与智能计算
招收计算机或微电子专业基础好、编程能力和动手能力强的硕士和博士研究生。





教育背景1999-07--2001-06中国科学院计算技术研究所博士学位
1996-09--1999-06中国科学院计算技术研究所硕士学位


工作经历
2008/10－今，中科院计算所，计算机体系结构国家重点实验室， 研究员
2009/08－2010/08，美国UCSB大学，电子与计算机工程系，访问教授
2001/10－2008/09，中科院计算所，网络室/中科院计算机系统结构重点实验室，副研究员（2002/03硕士生导师，2006/03博士生导师）
2001/07－2001/09，中科院计算所，网络室，助理研究员



社会兼职2019-10-16-今,中国计算机学会集成电路设计专业组, 秘书长
2019-05-01-今,IEEE International Test Conference, Organizing Committee Member
2018-10-27-2020-12-31,IEEE VLSI Test Symposium, Publicity Co-Chair
2018-08-13-今,中国计量测试学会集成电路测试专业委员会, 副主任兼秘书长
2018-01-01-2018-12-31,IEEE ATS'18, Program Co-Chair
2017-09-15-2018-09-15,IEEE ITC-Asia'18, Program Co-Chair
2016-12-31-2017-12-30,第十七届全国容错计算学术会议, 大会主席
2016-12-30-2019-12-31,IEEE ATS指导委员会, 副主席
2016-01-01-2019-12-31,中国计算机学会容错计算专业委员会, 主任
2016-01-01-今,中国计算机学会, 理事
2014-12-31-2020-12-31,IEEE Trans. on VLSI Systems, Associate Editor
2014-01-01-今,《计算机研究与发展》, 编委
2013-12-31-2016-12-30,IEEE WRTLT指导委员会, 主席
2010-01-01-今,《计算机辅助设计与图形学学报》, 编委
2007-12-29-2015-12-30,中国计算机学会容错计算专业委员会, 秘书长


教授课程VLSI测试与可测试性设计
数字系统的故障诊断与可靠设计
数字系统的故障诊断与容错设计


指导学生已指导学生
张飞飞硕士研究生081201-计算机系统结构
范小鑫硕士研究生081201-计算机系统结构
靳松博士研究生081201-计算机系统结构
裴颂伟博士研究生081201-计算机系统结构
付祥博士研究生081201-计算机系统结构
付斌章博士研究生081201-计算机系统结构
张颖博士研究生081201-计算机系统结构
杨志硕士研究生081201-计算机系统结构
王颖博士研究生081201-计算机系统结构
许达文博士研究生081201-计算机系统结构
方运潭博士研究生081201-计算机系统结构
朱雪峰硕士研究生081201-计算机系统结构
刘辉聪硕士研究生081201-计算机系统结构
程云博士研究生081201-计算机系统结构
周艳红博士研究生081201-计算机系统结构
孙发强博士研究生081201-计算机系统结构
徐杰硕士研究生085211-计算机技术
刘国培硕士研究生081201-计算机系统结构
邓家超硕士研究生081201-计算机系统结构
现指导学生
晁会娜博士研究生081201-计算机系统结构
唐忆滨博士研究生081201-计算机系统结构
汪雍琛硕士研究生081201-计算机系统结构
邹凯伟博士研究生081201-计算机系统结构
杨玉鑫硕士研究生081201-计算机系统结构
陈国庆硕士研究生085211-计算机技术
田鹏宇硕士研究生081201-计算机系统结构
梁胜文博士研究生081201-计算机系统结构
赵文清硕士研究生081201-计算机系统结构
何银涛博士研究生081201-计算机系统结构

发表论文




[1] Ying Wang, Huawei Li, Long Cheng, Xiaowei Li, "A QoS-QoR Aware CNN Accelerator Design Approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.38, No.11, pp. 1995-2007, 2019.
[2] Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li, “Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.38, No.4, pp.767-779, 2019.
[3] Wen Li, Ying Wang, Huawei Li, Xiaowei Li “RRAMedy: Protecting ReRAM-based Neural Network from Permanent and Soft Faults During Its Lifetime,” Prof. of IEEE 37th International Conference On Computer Design (ICCD), 2019. BEST PAPER AWARD
[4] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-Processors,” IEEE 2nd International Test Conference in Asia (ITC-Asia), pp.73-78, 2018. BEST PAPER AWARD
[5] Ying Wang, Huawei Li, Xiaowei Li, “A Case of On-chip Memory Sub-system Design for Low-Power CNN Accelerators,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.1971-1984, 2018.
[6] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “On Trace Buffer Reuse based Trigger generation in Post Silicon Debug,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.2166-2179, 2018.
[7] Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multi-Processors,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.6, pp.1265-1277, 2018.
[8] Haihua Shen, Hua-Zhe Tan, Huawei Li, Feng Zhang, Xiaowei Li, “LMDet: A “Naturalness” Statistical Method for Hardware Trojan Detection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.26, No.4, pp.720-732, 2018.
[9] Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, and Xiaowei Li, “Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 10, pp.2736-2748, 2017.
[10] Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li, “Approximate STT-RAM Buffer Design for General Purpose Neural Network Accelerator”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.25, No.4, pp. 1285-1296, 2017.
[11] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.
[12] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016.
[13] Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.
[14] Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors,” IEEE Transactions on Computers (TC), Vol. 65, No.3, pp.716-729, 2016.
[15] Yintao He, Ying Wang, Huawei Li, Xiaowei Li “An Agile Precision-Tunable CNN Accelerator based on ReRAM,” Prof. of IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2019.
[16] Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li. “Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval,” Proc. of USENIX Annual Technical Conference (ATC), Renton, USA, pp.395-410, 2019.
[17] Yongchen Wang, Ying Wang, Huawei Li, Shi Cong, Xiaowei Li, “Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Activity Recognition”, Proc. of IEEE/ACM 56th Design, Automation Conference (DAC), USA, 2019, Article No. 210.
[18] Ying Wang, Shenwen Liang, Huawei Li, Xiaowei Li, “A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs”, Proc. of IEEE/ACM 56th DAC, USA, 2019, Article No. 202.
[19] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Lightweight Timing Channel Protection for Shared DRAM Controller,” Proc. of IEEE 49th International Test Conference (ITC), 2018.
[20] Dawen Xu, Kiajie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li, “FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors,” Prof. of IEEE 37th International Conference On Computer Aided Design (ICCAD), USA, Nov. 2018
[21] Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li, “XORiM: A Case of In-Memory Bit-Comparator Implementation and Its Performance Implications,” Prof. of ASP-DAC 2018, Paper 4B-4.
[22] Ying Wang, Huawei Li, Xiaowei Li, “Real-Time meets Approximate Computing: An Elastic Deep Learning Accelerator Design with Adaptive Trade-off between QoS and QoR,” Proc. of IEEE/ACM 54th Design Automation Conference (DAC), Austin, USA, June 2017, Article No. 33.
[23] Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhur, Insik Yoon, “Test and Reliability of Emerging Non-Volatile Memories,” Proc. of2017 IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, Nov. 27-30, 2017, pp.170-178.
[24] Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang, “Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking,” Prof. of IEEE 48th International Test Conference (ITC), USA, Paper 11.1, Oct.-Nov. 2017.
[25] Huawei Li, Xiaowei Li, “Formal Verification Practices in Industry,” in Proceedings of IEEE 35th VLSI Test Symposium (VTS), Paper 10C, Las Vegas, USA, April 2017.
[26] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug,” Proc. of IEEE 35th VLSI Test Symposium (VTS), Paper 3A-2, USA, April 2017.
[27] Ying Wang, Huawei Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” Prof. of IEEE International Conference On Computer Aided Design (ICCAD), USA, Nov. 2016.
[28] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family”, Proc. of 53rd IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2016.
[29] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors”, Proc. of 53rd IEEE/ACM Proceedings of Design, Automation Conference (DAC), USA, 2016.
[30] Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” Prof. of IEEE 47th International Test Conference (ITC), USA, Paper 16.2, Nov. 2016.
[31] Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, Proc. of IEEE 34th VLSI Test Symposium (VTS), Paper 1B-2, USA, April 2016.
[32] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016.
[33] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.
[34] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.
[35] Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.
[36] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.
[37] Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.
[38] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.
[39] Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.
[40] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.
[41] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc. of IEEE 31st VLSI Test Symposium (VTS), Paper 10B-3, Berkeley, CA, USA, May 2013.
[42] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247.
[43] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.
[44] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.
[45] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.
[46] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.
[47] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", Proc. of IEEE 29th VLSI Test Symposium (VTS), 2011, pp.272-277.
[48] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. of IEEE International Symposium on VLSI Design, Automation and Test, Taiwan, 2011.
[49] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” Proc. of IEEE 41st International Test Conference (ITC), Paper 12.1, Austin, USA, Oct. 2010.
[50] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” Proc. of IEEE 28th VLSI Test Symposium (VTS), Santa Cruz, USA, May 2010, pp.3-8.
[51] Songwei Pei, Huawei Li, Xiaowei Li, “An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing”, Proc. of Design Automation and Test in Europe (DATE), France, Mar. 2010, pp.1353-1356.
[52] Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” Proc. of IEEE 24th VLSI Test Symposium (VTS), Berkeley, CA, USA, May 2006.
[53] Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No.2, 2005, pp.181-195.
[54] Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” Proc. of IEEE 12th Asian Test Symposium (ATS), Xi'an, China, Nov. 2003, pp.178-183.
[55] Huawei Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,” Journal of Electronic Testing: Theory and Applications, Vol.16, No.5, Oct. 2000, pp. 477-485.








近期科研项目
国家自然科学基金面上项目：面向物端应用的深度学习处理器自动设计技术，2019/01-2022/12。



国家自然科学基金重点项目：差错容忍计算器件基础理论和方法，2015/01-2019/12。
国家自然科学基金面上项目：考虑时延变异性的硅后定时验证方法，2012/01-2015/12。
国家973课题：高性能处理芯片的设计验证与测试，2005/12-2010/12。
国家自然科学基金面上项目：避免过度测试的时延测试方法，2008/01-2010/12。
国家自然科学基金面上项目：面向串扰的时延测试，2007/01-2009/12。
国家863项目：可信计算平台软硬件系统安全测试评估模型、测试方法以及测试自动化技术，2007/07-2009/12。