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带有p型岛的超低导通电阻绝缘体上硅器件新结构\r\n\t\t

本站小编 Free考研考试/2022-01-16

\r代红丽1, 2, 3,赵红东1,王洛欣2,石艳梅2,李明吉2,李宇海\r3\r
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AuthorsHTML:\r代红丽1, 2, 3,赵红东1,王洛欣2,石艳梅2,李明吉2,李宇海\r3\r
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AuthorsListE:\rDai Hongli1, 2, 3,Zhao Hongdong1,Wang Luoxin2,Shi Yanmei2,Li Mingji2,Li Yuhai\r3\r
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AuthorsHTMLE:\rDai Hongli1, 2, 3,Zhao Hongdong1,Wang Luoxin2,Shi Yanmei2,Li Mingji2,Li Yuhai\r3\r
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Unit:\r\r1. 河北工业大学电子信息工程学院,天津 300401;\r
\r\r2. 天津理工大学电气电子工程学院,天津 300384;
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\r3. 光电信息控制和安全技术重点实验室,天津 300308\r
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Unit_EngLish:\r1. School of Electronics Information Engineering,Hebei University of Technology,Tianjin 300401,China;
2. School of Electrical and Electronic Engineering,Tianjin University of Technology,Tianjin 300384,China;
3. Key Laboratory of Electro-Optical Information Control and Security Technology,Tianjin 300308,China\r
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Abstract_Chinese:\r为了减小绝缘体上硅(SOI)器件的比导通电阻,提高器件的击穿电压,提出一种带有p 型岛的SOI 器件新结构.该结构的特征如下:首先,漂移区周围采用U 型栅结构,在开启状态下,U 型栅侧壁形成高密度电子积累层,提供了一个从源极到漏极低电阻电流路径,实现了超低比导通电阻;其次,在漂移区引入的氧化槽折叠了漂移
区长度,大大提高了击穿电压;最后,在氧化槽中引入一个p 型岛,该高掺杂p 型岛使漂移区电场得到重新分配,提高了击穿电压,且p 型岛的加入增大了漂移区浓度,使器件比导通电阻进一步降低.结果表明:在最高优值条件下,器件尺寸相同时,相比传统SOI 结构,新结构的击穿电压提高了140%,比导通电阻降低了51.9%.\r
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Abstract_English:\rAn ultralow specific on-resistance(Ron,sp)of a silicon on insulator(SOI)device with a p-type island is proposed to reduce the specific on-resistance and improve the breakdown voltage of an SOI device. The device has the following features. First,a U-shaped gate is installed around the drift region. In the on-state,the U-shaped gate induces a high-density electron accumulation layer along the sidewall,which provides a low-resistance current path from the source to the drain,to achieve an ultralow R on,sp. Second,an oxidation trench is introduced into the drift region. This oxidation trench can fold the drift region length,which considerably increases the breakdown voltage. Finally,a p-type island is introduced. The highly doped p-type island redistributs the drift region electric field, which improves the breakdown voltage. The addition of the p-type island also increases the drift region concentration,which further decreases the device R on,sp. Simulation results show that under the condition of the highest FOM,the breakdown voltage is increased by 140%,and the specific on-resistance is reduced by 51.9% compared with a conventional SOI device at the same cell pitch.\r
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Keyword_Chinese:绝缘体上硅;击穿电压;比导通电阻\r

Keywords_English:silicon on insulator(SOI);breakdown voltage;specific on-resistance\r


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