qiangliu@tju.edu.cn
未公开
教授
45纳米以下大规模集成电路布局布线同步优化方法的研究

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面向安全的集成电路新型设计和优化方法研究

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具有IP保护特质的集成电路系统新型设计方法研究

A 66.1 Gbps single-pipeline AES on FPGA

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Hardware Trojan Detection Acceleration Based on Word-Level Statistical Properties Management

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Optimizing designs by combining model-based and pattern-based transformations

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Neural Network Based Pre-placement Wirelength Estimation

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Automatic on-chip memory minimization for data reuse

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Heterogeneous systems for energy efficient scientific computing

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Convex models for accelerating applications on FPGA-based clusters

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Combining optimizations in automated low power design

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Automatic optimisation of mapreduce designs by geometric programming

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Objective-driven workload allocation in heterogeneous computing systems

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Power adaptive computing system design in energy harvesting environment

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Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

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一种用于NoC知识产权的积极保护方法

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High throughput and secure AES on FPGA with fine pipelining

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Feedforward neural network models for FPGA routing channel width estimation

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Power-adaptive computing system design for solar-energy-powered embedded systems

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基于路径延时匹配的硬件IP核知识产权保护方法

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Review on Productivity Improvement of SoC Hardware Verification

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Automated mapping of the mapreduce pattern onto parallel computing platforms

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Optimizing hardware design by composing utility-directed transformations

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Comments on "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms"

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Compiling C-like languages to FPGA hardware: some novel approaches targeting data memory organization

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Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: a geometric programming framework

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Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems