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基本信息 The basic information
姓名: 胡伟

学院: 网络空间安全学院


学历: 博士研究生毕业

学位: 工学博士


职称: 副教授

职务:


学科: 网络空间安全


邮箱: weihu@nwpu.edu.cn




综合介绍 General Introduction
现为西北工业大学网络空间安全学院副教授，硕士生导师，分别于2005年、2008年和2012年获得该校学士、硕士和博士学位。2009年9月至2011年9月在加州大学圣迭戈分校计算机科学与工程系Ryan Kastner教授实验室作访问研究生；2014年5月至2017年5月在Kastner教授实验室作博士后研究工作。其研究方向主要包括硬件安全、形式化安全验证方法、密码学和可重构计算等。



科学研究 Scientific Research
硬件信息流安全、形式化安全验证、安全漏洞检测、硬件木马检测、旁路道分析、密码学、可重构计算




学术成果 Academic Achievements
专著教材
[1] 胡伟，慕德俊. 门级信息流分析理论与应用，科学出版社，2014.
[2] 胡伟，王馨慕，毛保磊，张慧翔，邰瑜. 硬件安全威胁与防范，西安电子科技大学出版社，2019.


会议论文
[1]Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. Theoretical Analysis of Gate Level Information Flow Tracking, ACM/EDAC/IEEE Design Automation Conference (DAC), 244-247, Jun. 2010.
[2]Ang Gao, Hairui Zhou, Yansu Hu, Dejun Mu, Wei Hu. Proportional delay differentiation service and load balancing in web cluster systems, IEEE Conference on Computer Communications Workshops (INFOCOM), 1-2, Mar. 2010.
[3]Ryan Kastner, Jason Oberg, Wei Hu, and Ali Irturk. Enforcing Information Flow Guarantees in Reconfigurable Systems with Mix-Trusted IP, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Jul. 2011. (invited paper)
[4]Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu and Ryan Kastner. An Improved Encoding Technique for Gate Level Information Flow Tracking, International Workshop on Logic & Synthesis (IWLS), Jun. 2011. (oral presentation)
[5]Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. Information Flow Isolation in I2C and USB, ACM/EDAC/IEEE Design Automation Conference (DAC), 254-259, Jun. 2011.
[6]Wei Hu, Jason Oberg, Dejun Mu, and Ryan Kastner. Simultaneous Information Flow Security and Circuit Redundancy in Boolean Gates, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 585-590, Nov. 2012.
[7]Baolei Mao, Wei Hu, Yu Tai, Huixiang Zhang and Dejun Mu. Secure hardware design through bit-tight information flow control, IEEE International Conference of IEEE Region 10 (TENCON 2013), 1-4, 2013.
[8]Baolei Mao, Wei Hu, Alric Althoff, Janarbek Matai, Jonathan Valamehr, Timothy Sherwood, Dejun Mu, and Ryan Kastner. Quantifying Timing-Based Information Flow in Cryptographic Hardware, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 552-559, Nov. 2015.
[9]Ryan Kastner, Wei Hu, and Alric Althoff. Quantifying Hardware Security Using Joint Information Flow Analysis, Design, Automation & Test in Europe Conference & Exhibition (DATE), 1523-1528, Mar. 2016. (invited paper)
[10]Wei Hu, Andrew Becker, Armita Ardeshiri, Yu Tai, Paolo Ienne, Dejun Mu, and Ryan Kastner. Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Article 95, Nov. 2016.
[11]Wei Hu, Alric Althoff, Armaiti Ardeshiricham, and Ryan Kastner. Towards Property Driven Hardware Security, Microprocessor Test and Verification Conference, 51-56, December 2016. (invited paper)
[12]Wei Hu, Lu Zhang, Armaiti Ardeshiricham, Jeremy Blackstone, Bochuan Hou, Yu Tai and Ryan Kastner. Why You Should Care About Don’t Cares: Exploiting Internal Don’t Care Conditions for Hardware Trojans, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 707-713, Nov 2017.
[13]Wei Hu, Armaiti Ardeshiricham and Ryan Kastner. Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities, 18th International Workshop on Microprocessor and SOC Test and Verification (MTV), Austin, TX, pp. 62-67, 2017.
[14]Andrew Becker, Wei Hu, Yu Tai, Phlip Brisk, Ryan Kastner and Paolo Ienne. Arbitrary Precision and Complexity Tradeoffs for Gate-level Information Flow Tracking, ACM/EDAC/IEEE Design Automation Conference (DAC), Article 5, June 2017.
[15]Armaiti Ardeshiricham, Wei Hu, Joshua Marxen and Ryan Kastner. Register Transfer Level Information Flow Tracking for Provably Secure Hardware Design, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1695-1700, Mar. 2017.
[16]Armaiti Ardeshiricham, Wei Hu and Ryan Kastner. Clepsydra: Modeling Timing Flows in Hardware Designs, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 147-154, Nov 2017.
[17]Yu Tai, Wei Hu, Lantian Guo, Baolei Mao and Dejun Mu. Gate Level Information Flow analysis for multi-valued logic system, 2nd International Conference on Image, Vision and Computing (ICIVC), Chengdu, pp. 1102-1106, 2017.
[18]Wei Hu, Armaiti Ardeshiricham, Mustafa S Gobulukoglu, Xinmu Wang, and Ryan Kastner. Property Specific Information Flow Analysis for Hardware Security Verification, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Article No. 89: 1-8, Nov. 2018.
[19]Wei Hu, Xinmu Wang, and Dejun Mu. Security Path Verification Through Joint Information Flow Analysis, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 415-418, Oct. 2018.
[20]Lu Zhang, Wei Hu, Armita Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu and Ryan Kastner. Examining the Consequences of High-Level Synthesis Optimizations on Power Side-Channel, IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1167-1170, Mar. 2018.
[21]Maoyuan Qin, Wei Hu, Dejun Mu and Yu Tai. Property Based Formal Security Verification for Hardware Trojan Detection, IEEE 3rd International Verification and Security Workshop (IVSW), Costa Brava, Spain, pp. 62-67, 2018.
[22]Wei Hu, Yixin Ma, Xinmu Wang and Xingxing Wang. Leveraging Unspecified Functionality in Obfuscated Hardware for Trojan and Fault Attacks, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi'an, China, pp. 1-6, Dec. 2019.
[23]Wei Hu, Linjuan Wu, Jing Tan, Yu Tai and Jiliang Zhang. A Unified Formal Model for Proving Security and Reliability Properties, Asian Test Symposium (ATS), Penang, Malaysia, pp. 1-6, Nov. 2020.
[24]Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye and Xiangqi Wang. HRAE: Hardware-assisted Randomization against Adversarial Example Attacks, IEEE 29th Asian Test Symposium (ATS), Penang, Malaysia, pp. 1-6, Nov. 2020.
[25]Dina G. Mahmoud, Wei Hu and Mirjana Stojilovic. X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs, 30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, pp. 185-192, 2020.
[26]Hang Liu, Chaofan Zhang, Hongming Fei, Wei Hu and Dawei Guo. Feedback-based Channel Gain Complement and Cluster-based Quantization for Physical Layer Key Generation, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Kolkata, India, 2020, pp. 1-6.
期刊论文
[1]Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. Theoretical Fundamentals of Gate Level Information Flow Tracking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30(8): 1128-1140, Aug. 2011.
[2]Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. On the Complexity of Generating Gate Level Information Flow Tracking Logic, IEEE Transactions on Information Forensics and Security (TIFS), vol. 7(3): 1067-1080, Jun. 2012.
[3]Tao Yang, Dejun Mu, and Wei Hu. Energy-Efficient Coverage Quality Guaranteed in Wireless Sensors Network, Applied Mathematics & Information Sciences, vol. 7(5): 1685-1691, 2013.
[4]Wei Hu, Jason Oberg, Dejun Mu, and Ryan Kastner. Expanding Gate Level Information Flow Tracking for Multi-level Security, IEEE Embedded Systems Letters (ESL), vol. 5(2): 25-28, 2013.
[5]Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. Gate Level Information Flow Tracking for Security Lattices, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20(1), Article 2, Nov. 2014.
[6]Dejun Mu, Wei Hu, Baolei Mao, and Bo Ma. A Bottom-up Approach to Verifiable Embedded System Information Flow Security, IET Information Security, vol. 8(1): 12-17, Jan. 2014.
[7]Tao Yang, Dejun Mu, Wei Hu and Huixiang Zhang. Energy-efficient border intrusion detection using wireless sensors network, EURASIP Journal on Wireless Communications and Networking 2014(1): 1-12.
[8]Wei Hu, Baolei Mao, Jason Oberg, and Ryan Kastner. Detecting Hardware Trojans with Gate-Level Information-Flow Tracking, IEEE Computer Special Issue on Security of Hardware and Software Supply Chain, vol. 49(8): 44-52, Aug. 2016.
[9]Yu Tai, Wei Hu, Huixiang Zhang, Dejun Mu, Xingli Huang. Generating optimized gate level information flow tracking logic for enforcing multilevel security, Automatic Control and Computer Sciences 50 (5), 361-368, 2016.
[10]Yu Tai, Wei Hu, Dejun Mu, Baolei Mao, Lantian Guo, Maoyuan Qin. A Simplifying Logic Approach for Gate Level Information Flow Tracking. In: Li B., Shu L., Zeng D. (eds) Communications and Networking. ChinaCom 2017. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 237. Springer, Cham., 2018.
[11]Yu Tai, Wei Hu, Dejun Mu, Baolei Mao and Lu Zhang. Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design, IEEE Access, vol. 6, pp. 1822-1831, 2018.
[12]Baolei Mao, Wei Hu, Alric Althoff, Janarbek Matai, Yu Tai, Dejun Mu, Timothy Sherwood, Ryan Kastner. Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(9): 1719-1732.
[13]毛保磊,胡伟,张慧翔,慕德俊,邰瑜,洪亮.基于信息熵的RSA硬件时间隐通道信息泄露量化研究.计算机学报, 2018, 41(2):426-438.
[14]Maoyuan Qin, Wei Hu, Xinmu Wang, Dejun Mu, Baolei Mao. Theorem Proof Based Gate Level Information Flow Tracking for Hardware Security Verification, Computers & Security, 85:225-239, Aug. 2019.
[15]Lu Zhang, Dejun Mu, Wei Hu, Yu Tai, Jeremy Blackstone, and Ryan Kastner. Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10): 2124-2137, 2020.
[16]Maoyuan Qin, Xinmu Wang, Baolei Mao, Dejun Mu, Wei Hu. A Formal Model for Proving Hardware Timing Properties and Identifying Timing Channels, Integration, the VLSI Journal, 72(C):123-133, May 2020.
[17]Lu Zhang, Dejun Mu, Wei Hu, and Yu Tai. Machine Learning based Side Channel Leakage Detection in Electronic System Level Synthesis, IEEE Network, 34(3): 44-49, 2020.
[18]Jeremy Blackstone, Wei Hu, Alric Althoff, Armaiti Ardeshiricham, Lu Zhang, Ryan Kastner. A Unified Model for Gate Level Propagation Analysis, arXiv preprint arXiv:2012.02791
[19]Wei Hu, Chip Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner and Hai Li. An Overview of Hardware Security and Trust: Threats, Countermeasures and Design Tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2020.**.
[20]王省欣，胡伟，谭静，朱嘉诚，唐时博．AES相关故障注入攻击．西安电子科技大学学报. Vol. 84(4): 1-9, 2021.
[21]Yu Tai, Wei Hu, Lu Zhang, Dejun Mu and and Ryan Kastner. A Multi-flow Information Flow Tracking Approach for Proving Quantitative Hardware Security Properties, Tsinghua Science and Technology, vol. 26, no. 1, pp. 62-71, Feb. 2021.
[22]Lixiang Shen, Dejun Mu, Guo Cao, Maoyuan Qin, Jiacheng Zhu and Wei Hu. Accelerating hardware security verification and vulnerability detection through state space reduction, Computers & Security, Vol. 103, 102167, 2021.
[23]Xinmu Wang, Tamzidul Hoque, Abhishek Basak, Robert Karam, Wei Hu, Maoyuan Qin, Dejun Mu, and Swarup Bhunia. Hardware Trojan Attack in Embedded Memory, ACM Journal on Emerging Technologies in Computing Systems, Vol. 17(1), Article 6, 28 pages, January 2021.
[24]Wei Hu, Armaiti Ardeshiricham and Ryan Kastner. Hardware Information Flow Tracking. ACM Computing Surveys, 2021. (in press)



团队信息 Team Information
邰瑜 研究员

武玲娟 博士后研究员


研究生：
朱嘉诚
马艺新
谭静
王省欣
郑健
李雪霏
高亦菲



学术活动 Professional Activities
[1]IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 客座副主编
[2]2019 IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 共同程序主席

[3]2019-2020 China Fault Tolerance Conference (CFTC) , 程序委员会成员, 分会主席
[4]2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 分会主席
[5]2018 International Conference on Computer Design (ICCD), 程序委员会成员
[6]2017-2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 组委会委员及程序委员会成员
[7]2017-2020 IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 组委会委员及程序委员会成员
[8]2017 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 程序委员会成员



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