付宇卓 / 教授、博导
研究方向：系统级芯片设计
电子邮箱：yzfu@sjtu.edu.cn
办公电话：**-1066
办公地点：微电子楼417室
个人简介
学术研究
授课教学
付宇卓，教授，博士生导师。1990年获得国防科技大学计算机系学士学位，1997年和2001分别获得哈尔滨工业大学计算机系统结构专业工学硕士和博士学位。2006年获教授职称，2010年获博导资格，华盛顿大学、康考迪亚大学访问****、加拿大Concordia大学客座教授。
发表国内外高水平论文100余篇，担任多个国际会议、核心期刊的审稿人。主持过国家863、上海市科委等课题，参与国家核、高、基重大科研项目，获得过2008年上海市领军人才荣誉，多次荣获上海交通大学优秀教师称号。
担任国家集成电路人才培养基地委员会委员、上海交通大学电类学部学位委员会委员、上海交通大学国家集成电路人才培养基地负责人、上海交通大学教学指导委员会委员、上海交通大学实践教学委员会主任委员；上海集成电路行业协会副理事长单位上海交通大学负责人、上海市科委领域预测专家、上海市经信委聘任专家、闵行区科委专家、紫竹科技园集成电路平台建设专家。
Prof. Yuzhuo Fu is leading the Innovative Computer Architecture and Technology Lab (iCAT) at Dept. of Micro/Nano Electronics, SJTU. He received B.S. degree from Computer Engineering Department at Changsha Institute of Technology, and M.S. and Ph.D. degrees from Computer Science and Engineering Department, Harbin Institute of Technology. Prior to joining SJTU in 2001, he worked as Senior Engineer for the electric engineering institute of Heilongjiang University and Computing Center of Heilongjiang Province. He is Present Deputy Professor of undergraduate student affair office of SJTU.

研究方向：
Fault tolerate architecture, heterogeneous system architecture, and edge computing architecture. Especially focused on application-driven design/architecture innovations, which include novel architectures for artificial intelligence (AI) and acceleration with CPU/GPU/FPGA.

主要论文：
焦佳佳, 付宇卓，可靠性感知的片上网络链路管理策略, 上海交大学报47卷第1期, 2013年1月.
韩兴，蒋江，付宇卓，动态可重构众核处理器仿真平台设计，上海交大学报47卷第1期, 2013年1月.
刘婷，乌耀益，付宇卓，片上网络任务映射算法的可靠性优化，上海交大学报47卷第1期, 2013年1月.
Jiao J, Fu Y. RAPA: reliability-aware priority arbitration strategy for network on chip[C]//Proceedings of the great lakes symposium on VLSI. ACM, 2012: 99-102.
Yaoyi Wu; Jiang Jiang; Jiajia Jiao; Xing Han, “Fault-Tolerant Flow Control with Dataflow Division in Network-on-Chip,” Fourth International Conference on Computational Intelligence and Communication Networks (CICN), pp.487,490, 3-5 Nov. 2012
Jiajia Jiao, Peng Wu, Yuzhuo Fu, Exploiting low cost reliability for NoC transient routing error, 3rd International Conference on Computer Technology and Development (ICCTD), 2011
Xiangming S, Yuzhuo F, Jiajia J, et al. Configurable Redundant Routing for Network on Chip[C]//Computational Intelligence and Communication Networks (CICN), 2012 Fourth International Conference on. IEEE, 2012: 477-479.
Jiao J, Fu Y, Jiang J. Architecture-level analysis and evaluation of transient errors on NoC[C]//NORCHIP, 2011. IEEE, 2011: 1-4.
Jiajia Jiao and Yuzhuo Fu. 2011. B2RAC: a physical express link addition methodology for network on chip. In Proceedings of the 4th International Workshop on Network on Chip Architectures (NoCArc ’11). ACM, New York, NY, USA, 17-22.
Jiajia Jiao; Yuzhuo Fu; Ting Liu; Han Wang; Xing Han; Jiafang Wang, “Performance analysis and optimization for homogenous multi-core system based on 3D Torus Network on Chip,” NEWCAS Conference (NEWCAS), 2010 8th IEEE International, pp.313,316, 20-23 June 2010
穆静,付宇卓,刘婷,. 片上网络中3D拓扑结构的性能评估[J]. 信息技术,2010,(5).
Jiajia Jiao; Yuzhuo Fu; Yaoyi Wu, “Multi-application Specified Link Removal Strategy for Network on Chip,” Computational Sciences and Optimization (CSO), 2011 Fourth International Joint Conference, pp.520,524, 15-19 April 2011
Han Wang; Yuzhuo Fu; Ting Liu; Jiafang Wang, “Thermal management via task scheduling for 3D NoC based multi-processor,” SoC Design Conference (ISOCC), pp.440,444, 22-23 Nov. 2010
Wenqi Bao; Jiang Jiang; Yuzhuo Fu; Qing Sun, “A reconfigurable macro-pipelined systolic accelerator architecture,” Field-Programmable Technology (FPT), pp.1,6, 12-14 Dec. 2011
Nanxiang Mei; Yuzhuo Fu; Ting Liu, “Distributed Shared Memory Architecture for NoC-Based Multi-Processor,” Computational Intelligence and Software Engineering(CiSE), pp.1,4, 11-13 Dec. 2009
Jiang Wang; Yuzhuo Fu; Liang Dong, “Modeling of UHF voltage multiplier for radio-triggered wake-up circuit,” . IEEE 10th Annual Wireless and Microwave Technology Conference (WAMICON ), pp.1,3, 20-21 April 2009

本科《数字集成电路设计》，《编译技术与算法设计引论》，《计算机组成》，《微电子学概论》
研究生《高等数字集成电路设计》