梁 晓峣 教授
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电子邮件：liang-xy@cs.sjtu.edu.cn
实验室： 先进计算机体系结构实验室


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工作经验
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Computer Architecture
GPGPU

2005/02-2008/12 Harvard University, Ph.D
2003/08-2004/12 State University of New York at Stony Brook, MS
1996/09-2000/06 Fudan University, B.Eng

012/04-present Shanghai Jiao Tong University, Professor

MS108, Computer System 1
CS427, Multicore Architecture and Parallel Computing
Journal Publications:
Zhuoran Song, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, XiaoyaoLiang, and Li Jiang.ITT-RNA: Imperfection Tolerable Training forRRAM-Crossbar based Deep Neural-network Accelerator.IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, (TCAD), 2020.

Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing,Weifeng Zhang, Xiaoyao Liang: Energy-Efficient and Quality-Assured ApproximateComputing Framework Using a Co-Training Method. ACM Transactions on DesignAutomation of Electronic Systems (TODAES) 24(6): 59:1-59:25 (2019)

Jianfei Wang , Qin Wang, Li Jiang, Chao Li , Xiaoyao Liang, and NaifengJing. IBOM: An Integrated and Balanced On-Chip Memory for High PerformanceGPGPUs. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS (TPDS), VOL. 29,NO. 3, MARCH 2018.

Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, and XiaoyaoLiang. Cnfet-based high throughput SIMD architecture. IEEE Trans. on CAD ofIntegrated Circuits and Systems (TCAD), 37(7):1331_1344, 2018.

L. Jiang, T. Li, N. Jing, N. Kim, M. Guo and Xiaoyao Liang,“CNFET-basedHigh Throughput SIMD Architecture”, IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems (TCAD), 2017.

Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, ChaoLi and Xiaoyao Liang, “Bank Stealing for a Compact and Efficient Register FileArchitecture in GPGPU”, IEEE Transactions on Very Large Scale IntegrationSystems (TVLSI), 2016.

Naifeng Jing, Li Jiang, Tao Zhang, Fengfeng Fan, Chao Li, Xiaoyao Liang,"Energy Efficient eDRAM-Based On-Chip Storage Architecture forGPGPUs," IEEE Transactions on Computers (TC), 2016.

Yu Wang, Weikang Qian, Shuchang Zhang, Xiaoyao Liang, Bo Yuan, "ALearning Algorithm for Bayesian Networks and Its Efficient Implementation onGPUs," IEEE Transactions on Parallel and Distributed Systems (TPDS), 2016.

T. Li, F. Xie, Xiaoyao Liang, Q. Xu, K.Chakrabarty, N. Jing and L.Jiang, “A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs”. IEEETransactionson Computer-Aided Design of Integrated Circuits andSystems (TCAD), 2016.

Tao Zhang, Jingjie Zhang, Wei Shu, Min-You Wu, Xiaoyao Liang,"Efficient Graph Computation on Hybrid CPU and GPU Systems," TheJournal of Supercomputing (TJSC), 2015.

Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, XiaoyaoLiang, "Buddy SM: Sharing Pipeline Front-End For Improved EnergyEfficiency In GPGPUs," ACM Transactions on Architecture and CodeOptimization (TACO), 2015.

Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “MicroFix:Using Timing Interpolation and Delay Sensors for Power Reduction,” ACMTransactions on Design Automation of Electronic Systems (TODAES), 2011.

Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “ReVIVaL, Variation TolerantArchitecture Using Voltage Interpolation and Variable Latency,” IEEE Micro TopPicks, 2009.

Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Replacing 6T SRAMswith 3T1D DRAMs in the L1 Data Cache to Combat Process Variability,” IEEE MicroTop Picks, 2008.


Conference Publications:
Zhuoran Song, Feiyang Wu, Xueyuan Liu, Jing Ke, Naifeng Jing, XiaoyaoLiang, “VR-DANN: Real-Time Video Recognition via Decoder-Assisted NeuralNetwork Acceleration”, IEEE/ACM International Symposium on Microarchitecture(MICRO), Oct. 2020.

Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, NaifengJing, Xiaoyao Liang.DRQ: Dynamic Region-Based Quantization for DeepNeural Network Acceleration. IEEE/ACM International Symposium on ComputerArchitecture (ISCA), 2020.

Zhuoran Song, Yilong Zhao, Yanan Sun, Xiaoyao Liang and Li Jiang.ESNreram:An Energy-Efficient Sparse Neural Network Based on Resistive Random-AccessMemory. ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020

Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang,Naifeng Jing.GPNPU: Enabling Efficient Hardware-Based Direct Convolution withMulti-Precision Support in GPU Tensor Cores. ACM/IEEE Design AutomationConference (DAC), 2020.

Jing Ke, Qiqing Shen, Yi Guo, Jason D. Wright, Xiaoyao Liang. A PredictionModel for Microsatellite Status from Histology Images. 2020 ACM 10thInternationalConference on Biomedical Engineering and Technology, 2020.

Jing Ke, Changchang Liu, Yizhou Lu, Naifeng Jing, Xiaoyao Liang, FusongJiang.FIMIL : A high-throughput deep learning model for abnormality detectionwith weak annotation in microscopy images.ACM International ConferenceProceeding Series,February 4, 2020,Proceedings of the AustralasianComputer Science Week Multiconference 2020.

Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, YunyanHong, Xiaoyao Liang, Yinhe Han and Li Jiang.PIM-Prune: Fine-Grain DCNNpruning for Crossbar-based Process-In-Memory architecture. To appear inACM/IEEE Design Automation Conference (DAC), 2020

Xiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao,Hai Cao, Yinhe Han, Xiaoyao Liang, Li Jiang. System level hardware failureprediction using deep learning. ACM/IEEE Design Automation Conference (DAC),Las vegas, US, 2019.

Jing Ke, Zhaoming Jiang, Changchang Liu, Tomasz Bednarz, Arcot Sowmya,Xiaoyao Liang. Selective Detection and Segmentation of Cervical Cells, 201911th International Conference on Bioinformatics and Biomedical Technology,2019.

Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke and XiaoyaoLiang. HUBPA: High Utilization Bidirectional Pipeline Architecture forNeuromorphic Computing. ACM/IEEE Asia South Pacific Design AutomationConference (ASPDAC) 2019.

Zhuoran Song, Dongyu Ru, Ru Wang, Hongru Huang, Zhenghao Peng, Jing Ke,Xiaoyao Liang, and Li Jiang. Approximate Random Dropout for DNN trainingacceleration in GPGPU. Design Automation and Test in Europe（DATE）, 2019.

Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing. ASharing-Aware L1.5D Cache for Data Reuse in GPGPUs. ACM/IEEE Asia South PacificDesign Automation Conference (ASPDAC) 2019.

Zhenghao Peng, Li Jiang, Xuyang Chen, Chengwen Xu, Naifeng Jing, XiaoyaoLiang and Cewu Lu. AXNet: ApproXimate computing using an end-to-end trainableneural network. Accepted by ACM/IEEE International Conference on Computer-AidedDesign (ICCAD) 2018.

Haiyue Song, Li Jiang, Chengwen Xu, Zhuoran Song, Naifeng Jing, XiaoyaoLiang and Qiang Xu. Invocation-driven Neural Approximate Computing with aMulticlass-Classifier and Multiple Approximators. Accepted by ACM/IEEEInternational Conference on Computer-Aided Design (ICCAD), 2018.

Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang,and Li Jiang. In-growth test for monolithic 3d integrated SRAM. In 2018 Design,Automation & Test in Europe Conference & Exhibition (DATE) 2018,Dresden, Germany, March 19-23, 2018, pages 569_572, 2018.

Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, XiaoyaoLiang, and Li Jiang. A FPGA friendly approximate computing framework withhybrid neural networks: (abstract only). In Proceedings of the 2018 ACM/SIGDAInternational Symposium on Field-Programmable Gate Arrays (FPGA) 2018,Monterey, CA, USA, February 25-27, 2018, page 286, 2018.

Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao LiangandLi Jiang,“On Quality Trade-off Control for Approximate Computing usingIterative Training”, ACM/IEEE Design Automation Conference (DAC), June. 2017.

Tianjian Li, Xiangyu Bi, Naifeng Jing, Yu Wang, Xiaoyao Liang andLiJiang,“Sneak-path based Test and Diagnosis for 1R RRAM Crossbar using VoltageBias Technique”, ACM/IEEE Design Automation Conference (DAC), June. 2017.

Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng,Jiyuan Shen,Xiaoyao Liang andLi Jiang, "Learning Variations and Defects: aNeural-network Retraining Method for Fault Tolerance in the RRAM Crossbar”,ACM/IEEE Design Automation & Test in Europe Conference and Exhibition(DATE), April. 2017.

Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. LeeandLiJiang, "Fault Clustering Technique for 3D Memory BISR”, ACM/IEEE DesignAutomation & Test in Europe Conference and Exhibition (DATE), April. 2017.

Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li,Xiaoyao Liang, “Cache-Emulated Register File: An Integrated On-Chip MemoryArchitecture for High Performance GPGPUs”, 49th Annual IEEE/ACM InternationalSymposium on Microarchitecture (MICRO), Oct. 2016.

Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang and Naifeng Jing,“Applying Victim Cache in High Performance GPGPU Computing”, InternationalSymposium on Parallel and Distributed Computing (ISPDC), 2016. (Best PaperAward)

Chao Li, Zhenhua Wang, Xiaofeng Hou, Haopeng Chen, Xiaoyao Liang, andMinyi Guo, “Power Attack Defense: Securing Battery-Backed Data Centers”, 43rdACM/IEEE Int. Symp. on Computer Architecture (ISCA), Jun. 2016.

Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu and Krishnendu Chakrabarty,”Defect Tolerance for CNFET-based SRAMs”, IEEE International Test Conference(ITC), 2016.

Tianjian Li, Li Jiang, Naifeng Jing, Namsung Kim, Xiaoyao Liang,“CNFET-Based High Throughput Register File Architecture”, InternationalConference on Computer Design (ICCD), 2016.

L. Jiang, X. Huang, H. Xie, Q. Xu, C. Li, Xiaoyao Liang and H. Li, “A NovelTSV Probing Technique with Adhesive Test Interposer”, International Conferenceon Computer Design (ICCD), Oct. 2015.

L. Jiang, P. Pang, N. Jing, S. K. Lim, Xiaoyao Liang and Q. Xu, "OnDiagnosable and Tunable 3D Clock Network Design for Lifetime ReliabilityEnhancement", International Test Conference (ITC), Oct. 2015.

T. Li, H. Chen, W. Qian, Xiaoyao Liang, and L. Jiang, "OnMicroarchitectural Modeling for CNFET-based Circuits", IEEE System On ChipConference (SOCC), Sep. 2015.

C. Wang, L. Jiang, T. Li, Xiaoyao Liang, W. Qian, "Timing-DrivenPlacement for Carbon Nanotube Circuits", IEEE System On Chip Conference(SOCC), Sep. 2015.

Weichao Tang, Yu Wang, Haopeng Liu, Tao Zhang, Chao Li, Xiaoyao Liang,“Exploring Hardware Profile-Guided Green Datacenter Scheduling,” InternationalConference on Parallel Processing (ICPP), September 2015.

Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, XiaoyaoLiang, “Bank Stealing For Conflict Mitigation in GPGPU Register File,”International Symposium on Low Power Electronics and Design (ISLPED), July2015.

Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang, “CGSharing:Efficient Content Sharing in GPU-Based Cloud Gaming,” International Symposiumon Low Power Electronics and Design (ISLPED), July 2015.

Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, Xiaoyao Liang,“Building Fuel Powered Supercomputing Data Center at Low Cost,” InternationalConference on Supercomputing (ICS), June 2015.

Chao Li, Longjun Liu, Yang Hu, Juncheng Gu, Mingcong Song, XiaoyaoLiang, Jingling Yuan, Tao Li, “Towards Sustainable In-Situ Server Systems inthe Big Data Era, ” International Symposium on Computer Architecture (ISCA),June 2015.

Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, NaifengJing, Li Jiang, "Jump Test for Metallic CNTs in CNFET-Based SRAM,"Design Automation Conference (DAC), June 2015.

Xiaodong Meng, Chentao Wu, Minyi Guo, Jie Li, Xiaoyao Liang, Long Zheng,Bin Yao, "HFA: A Hint Frequency-based Approach to Enhance the I/OPerformance of Multi-level Cache Storage Systems," 20th IEEE InternationalConference on Parallel and Distributed Systems (ICPADS), December 2014.

Tao Zhang, Xiaoyao Liang, "Dynamic Front-End Sharing in GraphicProcessing Units," International Conference on Computer Design (ICCD),October 2014.

Mingyang Yang, Bin Yao, Yingkai Li, Jinsong Bao, Yao Shen, Jingyu Zhou,Chentao Wu, Feilong Tang, Minyi Guo, Xiaoyao Liang, Li Li,“Spatio-Textualk Nearest Neighbor Joins using MapReduce,” International Conference on Big Dataand Smart Computing (BigComp), February 2014 .

Bin Yao, Yue Yin, Jinsong Bao, Yao Shen, Jingyu Zhou, Chentao Wu, FeilongTang, Minyi Guo, Xiaoyao Liang, Li Li,“An Index Framework for DistributedData Warehouse,” International Conference on Big Data and Smart Computing(BigComp), February 2014.

Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang, “Compiler AssistedDynamic Register File in GPGPU,” International Symposium on Low PowerElectronics and Design (ISLPED), August 2013.

Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, MinyiGuo, Ramon Canal, Xiaoyao Liang, “An Energy-Efficient and Scalable eDRAM-BasedRegister File Architecture for GPGPU”, International Symposium onComputer Architecture (ISCA), June 2013.

Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao liang,“AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon forPower Efficiency in a Multicore Architecture”, International Symposium on HighPerformance Computer Architecture (HPCA), February 2012.

GuihaiYan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, “Leveraging theCore-Level Driven Complementary Effects of PVT Variations to Reduce TimingEmergencies in Multi-Core Processors,” International Symposium on ComputerArchitecture (ISCA), June 2010.

Kristen Lovin, Benjamin Lee, Xiaoyao Liang, Gu-Yeon Wei, DavidBrooks, “Empirical Performance Models for 3T1D Memories,” InternationalConference on Computer Design (ICCD), October 2009.

Xiaoyao Liang, Benjamin Lee, David Brooks, Gu-Yeon Wei, “Design and TestStrategies for Microarchitectural Post-Fabrication Tuning,” InternationalConference on Computer Design (ICCD), October 2009.

Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “MicroFix:Exploiting Path-Grained Timing Adaptability for ImprovingPower-Performance Efficiency,” International Symposium on Low Power Electronicsand Design (ISLPED), August 2009.

Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “DRAM-based On-ChipCache Architectures to Combat Process Variations,” Intel 2008 European Researchand Innovation Conference, September 2008.

Gu-Yeon Wei, David Brooks, A. Durlov Khan, Xiaoyao Liang, “Instruction-DrivenClock Scheduling with Glitch Mitigation,” International Symposium on Low PowerElectronics and Design (ISLPED), August 2008.

Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “ReVIVaL: A Variation TolerantArchitecture Using Voltage Interpolation and Variable Latency,” InternationalSymposium on Computer Architecture (ISCA), June 2008.

Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “A Process-Variation-TolerantFloating-Point Unit with Voltage Interpolation and Variable Latency,” IEEEInternational Solid State Circuit Conference (ISSCC), February 2008.

Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process VariationTolerant 3T1D-based Cache Architectures,” 40th International Symposium onMicroarchitecture (MICRO), December 2007.

Xiaoyao Liang, Kerem Turgay, David Brooks, “Architectural Power Models forSRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques,”International Conference on Computer Aided Design (ICCAD), November 2007.

Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process VariationTolerant Register Files Based on Dynamic Memories,” Workshop on ArchitecturalSupport for Gigascale Integration (ASGI), in conjunction with ISCA 2007, June2007.

Xiaoyao Liang, David Brooks, “Mitigating the Impact of Process Variationson CPU Register File and Execution Units,” 39th International Symposium onMicroarchitecture (MICRO), December 2006.

Xiaoyao Liang, David Brooks, “Microarchitecture Parameter Selection toOptimize System Performance under Process Variation,” International Conferenceon Computer Aided Design (ICCAD), November 2006.

Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks,“Design and Implementation of An Ultra Low Power System Architecture forWireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - PhaseII, 1st place, October 2006.

Xiaoyao Liang, David Brooks, “Latency Adaptation for Multi-ported RegisterFiles to Mitigate the Impact of Process Variations,” Workshop on ArchitecturalSupport for Gigascale Integration (ASGI), in conjunction with ISCA 2006, June2006.

Xiaoyao Liang, David Brooks, “Highly Accurate Power Modeling Method forSRAM Structures with Simple Circuit Simulation,” The Second Watson Conferenceon Interaction between Architecture, Circuits, and Compilers (p=ac2), September2005.

Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Equalizing Execution Pathfor Processing Speed Determination in Block Level Pipelining,” IEEEInternational Symposium on Circuits and Systems (ISCAS), May 2005.

Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Dynamic Corse GrainDataflow Reconfiguration Technique for Real-Time System Design,” IEEEInternational Symposium on Circuits and Systems (ISCAS), May 2005.

Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks,“Design and Implementation of An Ultra Low Power System Architecture forWireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - PhaseI, 2nd place, October 2005.

Yulei Weng, Sankalp Kallakuri, Xiaoyao Liang, Alex Doboli, et. al,“Dynamic Architecture Adaptation to Improve Scalability of Sensor Networks: ACase Study for a Smart Sensor for Face Recognition,” 25th IEEE InternationalReal-Time Systems Symposium(RTSS), December, 2004.

Sangjin Hong, Xiaoyao Liang, Petar Djuric, “Reconfigurable Particle FilterDesign Using Dataflow Structure Translation”, IEEE Workshop on SignalProcessing Systems (SIPS), September 2004.

Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Data CentricSIR Particle Filter Design Using Buffer-level Pipelining”, 7th InternationalConference on Signal Processing (ICSP), August 2004.

Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Design andSynchronization of Gaussian Particle Filter Using Distributed ControllerScheme”, 7th International Conference on Signal Processing (ICSP), August 2004.

Sangjin Hong, Magesh Sadasivam, Xiaoyao Liang, “Post-Generation of OverallExecution Controller for Data Centric Signal Processing Algorithms,” 7thInternational Conference on Signal Processing (ICSP), August 2004.








Awarded SJTU New Teaching Star 2014
Awarded Shanghai May 4th Youth Medal 2014
Awarded CCF-Intel Young Faculty/Researcher Honor Program 2013
Won 1st Prize of SJTU All English Teaching Competition 2013
Two papers selected into IEEE Micro’s “Top Picks in Computer Architecture” special issues. “Top Picks” is awarded to 10 most outstanding and industry relevant papers from all top architecture conferences annually 2008, 2009
One paper was nominated for best paper award at ISLPED 2008
One paper was nominated for CACM special issue by SIGMICRO 2007
Won 1st prize of SRC SoC IC Design Challenge, awarded to the champion of 38 teams from top American universities 2005-2006

Associate Editor of Frontiers of Computer Science (FCS)
Editor of Communication of CCF (CCCF)
Reviewer of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
Reviewer of IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
Reviewer of IEEE Transactions on Computers (TC)
Reviewer of ACM Transactions on Architecture and Code Optimization (TACO)
PC of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
PC of International Symposium on Low Power Electronics and Design (ISLPED)
PC of IEEE International Symposium on Workload Characterization (IISWC)
PC ofInternational Symposium on Computer Architecture (ISCA)
PC of IEEE International Symposium on High Performance Computer Architecture (HPCA)
PC of High Performance Computing Conference (HiPC)