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科学研究
部分论文
1. Shiheng Yang, J. Yin, Haidong Yi, W-H Yu, P-I. Mak and R. P. Martins, “A 0.2-V Energy-Harvesting BLE Transmitter with a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28nm CMOS,” IEEE J. Solid-State Circuits (JSSC)，vol. 54, no. 5, pp. 1351–1362, May. 2019.
2. Shiheng Yang, J. Yin, P-I. Mak and R. P. Martins, “A 0.0056-mm2 -249-dB-FOM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring-VCOs,” IEEE J. Solid-State Circuits (JSSC)，vol. 54, no. 1, pp. 88–98, Jan. 2019.（Invited Paper）
3. Shiheng Yang, J. Yin, P-I. Mak and R. P. Martins, “A 0.0056mm2 All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fsrms Jitter and -249dB FOM,”ISSCC, Dig. Tech. Papers, Feb. 2018, pp. 118-119.（Chip Olympics, Highlight）
4. J. Yin, Shiheng Yang, H. Yi, W-H. Yu, P-I. Mak and R. P. Martins, “A 0.2V Energy-Harvesting BLE Transmitter with a Micropower System Efficiency at 0dBm Output and 5.2nW Sleep Power in 28nm CMOS,”ISSCC, Dig. Tech. Papers, Feb. 2018, pp. 450-451. （Chip Olympics）
5. Zunsong Yang, Yong Chen, Shiheng Yang, P-I Mak and R. P. Martins, “A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur,” ISSCC, Dig. Tech. Papers, Feb. 2019, pp. 270-271. （Chip Olympics）



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