职称：教授

办公室：四牌楼李文正楼中401

办公电话：

Email：qshu@seu.edu.cn

学习经历：

1981年/9月-1985年/6月安徽大学本科
1987年/9月-1990年/6月安徽大学硕士
1994年/9月-1997年/6月上海交通大学博士
1997年/9月-1999年/6月中国科学技术大学博士后

工作经历:

1999年/6-2002年/3月中兴通讯南京研究所
2002年/3-2003年/3月香港科技大学
2003年/3-现在东南大学信息学院

教授课程：

专用集成电路--本科课程
VLSI设计—博士课程

研究方向：

1、通信电路与系统
2、通信专用芯片设计
3、数模混合高速电路设计

获奖情况：


论文著作：

专著
[1]专用集成电路设计. 电子工业出版社. 2015.9
[2]模拟CMOS电路设计折中与优化. 电子工业出版社. 2013.5
主要论文
[1]10 Gb/s transmit equalizer using duobinary signaling over FR4 backplane[J]. High Technology Letters,v 23, n 3,p 266-270,September 1, 2017
[2]一个用于背板通信的24Gb/s高速自适应组合均衡器[J]. 电子学报, 2017, Vol. 45, no 7: 1608-1612
[3]应用于高速串行链路的噪声预测部分响应最大似然均衡[J]. 东南大学学报(自然科学版)
[4]High speed and reliability gearbox for 100GE physical coDing sublayer[J]. Electronics Letters,v 52, n 11,p 908-909,May 26, 2016
[5]A 10 Gb/s combined equalizer in 0.18 μm CMOS technology for backplane communication[J]. High Technology Letters,v 21, n 2,p 205-211,June 1, 2015
[6]A 14.5 Gb/s word alignment circuit in 0.18 μm CMOS technology for high-speed SerDes[J]. High Technology Letters,v 20, n 3,p 328-332,September 1, 2014
[7]A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes[J]. Journal of Semiconductors,v 34, n 12,December 2013
[8]40Gbps甚短距离并行光传输技术与实验系统[J].电子学报, 2011, Vol.39, no.5:1174-1177
[9]A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture[J]. Journal of Semiconductors,v 32, n 4,April 2011
[10]IBIS-AMI based PAM4 signaling and FEC technique for 25 Gb/s serial link[C]. Wired/Wireless Internet Communications 2017
[11]A 20 Gb/s wireline receiver with adaptive CTLE and half-rate DFE in 0.13 μm technology[C]. Wired/Wireless Internet Communications 2017
[12]A 10Gb/s partial response equalizer in 0.18μm CMOS using duobinary signaling[C]. Proceedings of SPIE - The International Society for Optical Engineering,v 10250,2017
[13]A noise predictive maximum likelihood equalization and its application in high speed serial link systems[C]. 6th International Workshop on Computer Science and Engineering, WCSE 2016,p 411-414,2016
[14]Optimization of equalization architecture for the high-speed serial communication[C]. Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID,v 2016-February,p 6-9,February 11, 2016
[15]Analysis and optimization of combined equalizer for high speed serial link[C]. Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID,v 2016-February,p 43-46,February 11, 2016
[16]Energy-efficient continuous-time linear equalizer for short-haul optical communications[C]. Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID,v 2016-February,p 76-80,February 11, 2016
[17]Partial response maximum likelihood equalization for high speed serial link systems[C]. 2015 Asia-Pacific Microwave Conference, APMC 2015
[18]A high-speed gearbox based on phase independent architecture for 100G Ethernet physical coding sublayer[C]. 2015 3rd International Conference on Information and Communication Technology, ICoICT 2015,p 251-254,August 31, 2015
[19]Design of a 6.25Gb/s adaptive decision feedback equalizer in 0.18μm CMOS technology[C]. 2014 IEEE Workshop on Advanced Research and Technology in Industry Applications, WARTIA 2014,p 1209-1212,December 4, 2014
[20]A 10ps 500MS/s two-channel Vernier TDC in 0.18um CMOS technology[C]. 2014 IEEE Workshop on Advanced Research and Technology in Industry Applications, WARTIA 2014,p 1268-1271,December 4, 2014
[21]A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration[C]. 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014,p 203-207,October 14, 2014
[22]An effective concatenated code encoding technique with reduced storage[C]. Applied Mechanics and Materials,v 543-547,p 2448-2451,2014
[23]10Gb/s orthogonally concatenated BCH encoder for fiber communications[C]. 2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation, IMSNA 2013,p1018-1021,2013
[24]Implementation of 10-Gb/s parallel BCH decoder based on virtex-5 FPGA[C]. Advanced Materials Research,v 429,p 159-164,2012
[25]10Gb/s RS-BCH concatenated encoder with pipelined strategies for fiber communication[C]. Advanced Materials Research,v 429,p 154-158,2012
[26]A high-speed and low-power up/down counter in 0.18-μm CMOS technology[C]. 2012 International Conference on Wireless Communications and Signal Processing, WCSP 2012
[27]A 6.25Gb/s adaptive analog equalizer in 0.18μm CMOS technology for high-speed SerDes[C]. Proceedings of 2nd International Conference on Computer Science and Network Technology, ICCSNT 2012,p 266-270,2012
[28]A 6.25Gbps adaptive decision feedback equalizer for serial data link in 0.18μm CMOS technology[C]. 2012 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2012

科研项目：

项目名称
[3]项目类别
[4]项目时间
[5]工作类别
[6]项目金额

高性能可扩展网络调度系统
国家自然科学基金面上项目
2005.01-2007.12
应用基础研究


40Gbps甚短距离并行光互连技术与实验系统
国家“863”项目
2006.12-2008.12
应用研究


10Gb/s EPON的FEC研究
横向项目
2008.4-2009.6
应用研究


10Gbps增强型前向纠错编码
横向项目
2009.2-2010.8
应用研究


TCP Proxy的开发与硬件实现
横向项目
2010.9-2011.7
应用研究


正交级联超强FEC 码研究
横向项目
2012.9-2013.10
应用研究


载波通信技术的研究与开发
横向项目
2013.10-2014.8
工程应用


基于以太网的高速载波通信系统开发
横向项目
2015.4-2017.4
工程应用


LTE 与物联网融合的机器通信芯片及其系统研究与开发
横向项目
2017.1-2018.12
应用研究


专利：

专利号
专利名称
专利类型

ZL 2.3
一种公平可扩展网络调度方法
发明专利授权


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