Architecture and Design Flow for a Highly Efficient Structured ASIC
Publication in refereed journal


香港中文大学研究人员 ( 现职)

潘江鹏教授 (电子工程学系)

蔡潮盛教授 (电子工程学系)

全文

数位物件识别号 (DOI) http://dx.doi.org/10.1109/TVLSI.2012.2190478

引用次数
Web of Sciencehttp://aims.cuhk.edu.hk/converis/portal/Publication/2WOS source URL

其它资讯

摘要As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a middle ground in price and performance between ASICs and field-programmable gate arrays (FPGAs) by sharing masks across different designs. In this paper, two sASIC architectures are proposed, the first being based on three-input lookup-tables, and the second on AOIhttp://aims.cuhk.edu.hk/converis/portal/Publication/2http://aims.cuhk.edu.hk/converis/portal/Publication/2 gates. The sASICs are programmed using a standard-cell compatible design flow. They are customized using a minimum of three masks, i.e., two metals and one via. The area and delay of the sASIC are compared with ASICs and FPGAs. Results over a set of benchmark circuits show that our AOIhttp://aims.cuhk.edu.hk/converis/portal/Publication/2http://aims.cuhk.edu.hk/converis/portal/Publication/2-based sASIC had an average of 1.76x/1.41x increase in area/delay compared to ASICs, a considerable improvement compared with the http://aims.cuhk.edu.hk/converis/portal/Publication/26.56x/5.09x increase for FPGAs. This is, to the best of our knowledge, the best performance reported in the literature for a practical sASIC. A prototype using the sASIC was fabricated using a universal machine control 0.13-mu m mixed-mode/RF process. It was fully verified using scan and functional tests, and used in a demonstration system.

着者Ho MH, Ai YQ, Chau TCP, Yuen SCL, Choy CS, Leong PHW, Pun KP
期刊名称IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版年份http://aims.cuhk.edu.hk/converis/portal/Publication/2013
月份3
日期1
卷号http://aims.cuhk.edu.hk/converis/portal/Publication/21
期次3
出版社Institute of Electrical and Electronics Engineers (IEEE)
页次4http://aims.cuhk.edu.hk/converis/portal/Publication/24 - 433
国际标準期刊号1063-8http://aims.cuhk.edu.hk/converis/portal/Publication/210
电子国际标準期刊号1557-9999
语言英式英语

关键词Application-specific integrated circuit (ASIC); area-delay comparison; field-programmable gate array (FPGA); structured-ASIC (sASIC); via-programmable
Web of Science 学科类别Computer Science; Computer Science, Hardware & Architecture; COMPUTER SCIENCE, HARDWARE & ARCHITECTURE; Engineering; Engineering, Electrical & Electronic; ENGINEERING, ELECTRICAL & ELECTRONIC