李平，博士，硕士生导师
Email：lipingstu@cqu.edu.cn
通信地址：重庆市沙坪坝区沙正街174号重庆大学A区主教1003
邮编：400044

李平，博士，分别于2014年和2018年获得电子科技大学微电子技术工程学士学位和微电子学与固体电子学工学博士学位。于2019年2月加入重庆大学微电子与通信工程学院从事教学和科研工作。主持国家级以及省部级科研项目两项，主研国家自然科学基金重点项目、重庆市自然科学基金重点项目等10余项。在IEEE Transaction on Electron Device、IEEE Electron Device Letters等学术期刊上发表多篇研究论文，授权中国发明专利2项。

主要研究功率半导体器件的工艺流程设计、芯片设计、应用与可靠性。目前科研的主要方向是与企业合作，从工艺流程设计、芯片参数仿真、流片验证、封装测试来研发具有完全自主知识产权的芯片。

欢迎相关专业同学加入课题组！

Publications
1. P. Li, J. W. Guo, Z. Lin, S. D. Hu, C. Shi, F. Tang, A Low-Reverse-Recovery-Charge Superjunction MOSFET With P-Base and N-Pillar Schottky Contacts. IEEE Transactions on Electron Devices, 2020.04 67(4): 1693-1698
2. P. Li, J. W. Guo, Z. Lin, S. D. Hu, F. Tang, A Low Reverse Recovery Charge Superjunction MOSFET With an Integrated Tunneling Diode. IEEE Transactions on Electron Devices, 2019.09, 66(10): 4309~4313
3. P. Li, J. J. Cheng, X. B. Chen. A TIGBT With Floating n-Well Region for High dV/dt Controllability and Low EMI Noise. IEEE Electron Device Letters, 2018, 39(4): 560-563.
4. P. Li, X. J. Lyu, J. J. Cheng, X. B. Chen. A Low On-State Voltage and Saturation Current TIGBT With Self-Biased pMOS. IEEE Electron Device Letters, 2016, 37(11): 1470-1472.
5. P. Li, M. F. Kong, X. B. Chen. A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current. IEEE 29th International Symposium on Power Semiconductor Devices and ICs, Prague, 2016, 307-310.
6. P. Li, J.J Cheng, X. B. Chen. Low on-state voltage and saturation current Trench Insulated Gate Bipolar Transistor with integrated Zener diode. Electronics Letters, 2017.11, 53(24): 1608~1610
7. P. Li, J.J Cheng, X. B. Chen. TIGBT with emitter-embedded gate for low turn-on loss and low electro-magnetic interference noise. Electronics Letters, 2018.09, 54(19): 1108~1110
8. P. Li, H. Huang, and X. Chen, “A low on-state voltage TIGBT with planar gate self-biased pMOS,” IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS), 12-15 Dec. 2017, pp. 456-459.
9. J. Cheng, W. Chen, J. Lin, P. Li, B. Yi, H. Huang, et al., “Potential of Utilizing High-k Film to Improve the Cost Performance of Trench LDMOS,” IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3049-3054, 2019.
10. J. Cheng, P. Li, W. Chen, B. Yi, and X. B. Chen, “Simulation Study of a Super-Junction Deep-Trench LDMOS With a Trapezoidal Trench,” IEEE Journal of the Electron Devices Society, vol. 6, no. pp. 1091-1096, 2018.




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