1.Multistage Latency Adders Architecture Employing Approximate Computing

Yang, XH, Xing, Y, Qiao, F, Yang, HZ

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS[0218-1266], Published 2017, Volume 26, Issue 3,

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2.Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

Jiang, HL, Han, J, Qiao, F, Lombardi, F

IEEE TRANSACTIONS ON COMPUTERS[0018-9340], Published 2016, Volume 65, Issue 8, Pages 2638-2644

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3.A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

Yang, XH, Huang, NY, Chen, YC, Qiao, F, Yang, HZ

IEICE ELECTRONICS EXPRESS[1349-2543], Published 2016, Volume 13, Issue 23,

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4.Approximate Computing of Remotely Sensed Data: SVM Hyperspectral Image Classification as a Case Study

Wu, YF, Yang, XH, Plaza, A, Qiao, F, Gao, LR, Zhang, B, Cui, YB

IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING[1939-1404], Published 2016, Volume 9, Issue 12, Pages 5806-5818

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5.媒体认知中的感知计算教学方法及平台建设研究

杨毅,钟娴,徐淑正,乔飞,王生进

计算机教育[1672-5913], Published 2016, Issue 12, Pages 159-162

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6.A precision-improved processing architecture of physical computing for energy-efficient SIFT feature extraction

Li, Yi, Qiao, Fei, Yang, Xinghua, Wei, Qi, Yang, Huazhong

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings[1520-6149], Published 2016, Volume 2016-, Pages 1041-1044

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7.An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm

Liu, Zheyu, Qiao, Fei, Wei, Qi, Yang, Xinghua, Li, Yi, Yang, Huazhong

Proceedings - International Symposium on Quality Electronic Design, ISQED[1948-3287], Published 2016, Volume 2016-, Pages 392-397

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8.A 14-bit 2.5-GS/s DAC using CAL-TRZ

Wu, Guoting, Wei, Qi, Chen, Xiayang, Qiao, Fei

2016 5th International Conference on Modern Circuits and Systems Technologies, MOCAST 2016, Published 2016,

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9.Approximate adder with hybrid prediction and error compensation technique

Yang, Xinghua, Xing, Yue, Qiao, Fei, Wei, Qi, Yang, Huazhong

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI[2159-3469], Published 2016, Volume 2016-, Pages 373-378

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10.A multi-accuracy-level approximate memory architecture based on data significance analysis

Chen, Yuanchang, Yang, Xinghua, Qiao, Fei, Han, Jie, Wei, Qi, Yang, Huazhong

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI[2159-3469], Published 2016, Volume 2016-, Pages 385-390

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11.A real-time and energy-efficient implementation of difference-of-Gaussian with flexible thin-film transistors

Wu, Nan, Liu, Zheyu, Qiao, Fei, Wei, Qi, Yang, Huazhong, Guo, Xiaojun, Xie, Yuan

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI[2159-3469], Published 2016, Volume 2016-, Pages 455-460

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12.Design methodology for approximate accumulator based on statistical error model

Liu, Chang,Yang, Xinghua,Qiao, Fei,Wei, Qi,Yang, Huazhong

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Published 2015, Pages 237-242

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13.媒体认知实验课程改革与实践

杨毅,徐淑正,乔飞,王靖淇,王生进

计算机教育[1672-5913], Published 2015, Issue 05, Pages 107-110

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14.媒体认知实验教学改革研究与探索

杨毅,徐淑正,乔飞,王靖淇,王生进

计算机教育[1672-5913], Published 2015, Issue 09, Pages 111-113

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15.媒体认知实验教学理念与实践研究

杨毅,徐淑正,乔飞,王靖淇,王生进

计算机教育[1672-5913], Published 2015, Issue 15, Pages 112-114

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16.A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage

Han, Xue,Zhao, Nan,Wei, Qi,Qiao, Fei,Yang, Huazhong,Wang, Hui

2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014, Published 2014, Pages 57-60

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17.A survey on low-complexity video coding methods and architectures

Yu, Shuang,Qiao, Fei,Yang, Xiao,Luo, Li,Yang, Huazhong

Recent Advances in Electrical and Electronic Engineering[2352-0965], Published 2014, Volume 7, Issue 1, Pages 26-36

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18.Design of Multi-stage Latency Adders Using Detection and Sequence-Dependence between Successive Calculations

Yang, Xinghua,Qiao, Fei,Liu, Chang,Wei, Qi,Yang, Huazhong

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)[0271-4302], Published 2014, Pages 998-1001

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19.Hardware acceleration with pipelined adder for support vector machine classifier

Liu, Chang,Qiao, Fei,Yang, Xinghua,Yang, Huazhong

2014 4th International Conference on Digital Information and Communication Technology and Its Applications, DICTAP 2014, Published 2014, Pages 13-16

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20.Increasing compression ratio of low complexity compressive sensing video encoder with application-Aware configurable mechanism

Yu, Shuang,Qiao, Fei,Luo, Li,Yang, Huazhong

International Conference on Communication and Signal Processing, ICCSP 2014 - Proceedings, Published 2014, Pages 995-998

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21.Library based image processing system with circuit-switched reconfigurable interconnection

Shao, Lu,Qiao, Fei,Li, Feitian,Luo, Li,Yang, Huazhong

International Conference on Communication and Signal Processing, ICCSP 2014 - Proceedings, Published 2014, Pages 1045-1049

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22.A hybrid cache architecture with 2D-based prefetching scheme for image and video processing

Zhou, Ni,Qiao, Fei,Yang, Huazhong

2013 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), Published 2013, Pages 1092-1096

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23.A novel redundant pipelined successive approximation register ADC

Fan, Hua,Wei, Qi,Qiao, Fei,Yang, Huazhong

IEICE ELECTRONICS EXPRESS[1349-2543], Published 2013, Volume 10, Issue 5, Pages -

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24.A novel video compression method based on underdetermined blind source separation

Liu, Jing,Qiao, Fei,Wei, Qi,Yang, Huazhong

Lecture Notes in Electrical Engineering[1876-1100], Published 2013, Volume 240 LNEE, Pages 13-20

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25.Design methodology of the heterogeneous multi-core processor with the combination of parallelized multi-core simulator and common register file-based instruction set extension architecture

Xia, Bingbing,Qiao, Fei,Yang, Huazhong,Wang, Hui

Journal of Computers (Finland)[1796-203X], Published 2013, Volume 8, Issue 2, Pages 356-364

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26.Design of Variable Latency Adder Based On Present and Transitional States Prediction

Yang, Xinghua,Qiao, Fei,Liu, Chang,Yang, Huazhong

2013 23RD INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), Published 2013, Pages 120-125

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27.Smart-Eyes: a FPGA-based smart camera platform with efficient multi-port memory controller

Xie, Kunzhi,Qiao, Fei,Qi, Wei,Yang, Huazhong,Luo, Li

PROCEEDINGS OF 3RD INTERNATIONAL CONFERENCE ON MULTIMEDIA TECHNOLOGY (ICMT-13)[1951-6851], Published 2013, Volume 84, Pages 1638-1647

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28.A "NEAR-THE-BEST" SYSTEM-LEVEL design methodology of MULTI-CORE h.264 video decoder based on the parallelized MULTI-CORE simulator

Xia, Bingbing,Qiao, Fei,Du, Zidong,Zhu, Di,Yang, Huazhong

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS[0218-1266], Published 2012, Volume 21, Issue 7, Pages -

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29.A PVT-aware and low power pulse-triggered flip-flop

Ma, Junjun,Qiao, Fei,Yang, Huazhong,Wang, Hui

Lecture Notes in Electrical Engineering[1876-1100], Published 2012, Volume 181 LNEE, Pages 11-20

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30.Balanced switching schemes for Gradient-Error compensation in Current-Steering dacs

Li, Xueqing,Wei, Qi,Qiao, Fei,Yang, Huazhong

IEICE TRANSACTIONS ON ELECTRONICS[0916-8524], Published 2012, Volume E95C, Issue 11, Pages 1790-1798

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31.Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine

Gao, Hongli,Qiao, Fei,Yang, Huazhong

MULTIMEDIA TOOLS AND APPLICATIONS[1380-7501], Published 2012, Volume 56, Issue 3, Pages 597-614

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32.Design methodology for multipliers with active leakage and dynamic power reduction

Tian, Xi,Qiao, Fei,Dong, Zaiwang,Liu, Yujun,Zhao, Yuting

Applied Mechanics and Materials[1660-9336], Published 2012, Volume 182-183, Pages 1440-1445

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33.Distributed smart camera network

Qi, Wei,Qiao, Fei,Yang, Huazhong

Recent Patents on Electrical Engineering[1874-4761], Published 2012, Volume 5, Issue 1, Pages 20-29

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34.Image dynamic-range enhancement based on human visual adaption mechanism

Yang, Minda,Qiao, Fei,Wei, Qi,Yang, Huazhong

Lecture Notes in Electrical Engineering[1876-1100], Published 2012, Volume 181 LNEE, Pages 1-9

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35.低功耗低电源线噪声纳米CMOS全加器

田曦,乔飞,董在望

微处理机[1002-2279], Published 2012, Issue 02, Pages 3-6

收录情况： CNKI

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36.An Efficient Methodology for Transaction-Level Design of Multi-core h.264 Video Decoder

Xia, Bingbing,Qiao, Fei,Yang, Huazhong,Wang, Hui

IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE 2011)[0747-668X], Published 2011, Pages 399-400

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37.Design of reconfigurable architectures for multi-standards video decoder

Tan, Sisi,Qiao, Fei,Yang, Hua Z.,Wang, Hui

Recent Patents on Electrical Engineering[1874-4761], Published 2011, Volume 4, Issue 1, Pages 63-70

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38.Low-power off-chip memory design for video decoder using embedded bus-invert coding

Zhou, Ni,Qiao, Fei,Yang, Huazhong,Wang, Hui

Proceedings - 2011 10th International Symposium on Autonomous Decentralized Systems, ISADS 2011, Published 2011, Pages 251-255

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39.System-level evaluation of video processing system using simplescalar-based multi-core processor simulator

Dut, Zidong,Xia, Bingbing,Qiao, Fei,Yang, Huazhong

Proceedings - 2011 10th International Symposium on Autonomous Decentralized Systems, ISADS 2011, Published 2011, Pages 256-259

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40.A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design

Xia, Bingbing,Qiao, Fei,Yang, Huazhong,Wang, Hui

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010, Published 2010, Pages 191-197

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41.An efficient 5/3-DWT based embedded compression algorithm for h.264 high definition decoder

Gao, Hongli,Qiao, Fei,Yang, Huazhong

2010 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS ICCE, Published 2010, Pages -

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42.Design of a highly parallel and double-level pipelined CAVLC encoder for H.264

Qiao, Fei,Qiao, Fei,Wei, Ding-Li,Wei, Ding-Li,Yang, Hua-Zhong,Yang, Hua-Zhong,Wang, Hui,Wang, Hui

Tien Tzu Hsueh Pao/Acta Electronica Sinica[0372-2112], Published 2010, Volume 38, Issue 7, Pages 1705-1710

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43.Effective memory architectures of multi-processor systems-on-chip

Zhou, Ni,Qiao, Fei,Yang, Huazhong,Wang, Hui

Recent Patents on Electrical Engineering[1874-4761], Published 2010, Volume 3, Issue 3, Pages 218-231

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44.Heterogeneous Multi-core systems for video processing

Xia, Bingbing,Qiao, Fei,Yang, Huazhong,Wang, Hui

Recent Patents on Electrical Engineering[1874-4761], Published 2010, Volume 3, Issue 3, Pages 200-210

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45.Low power cache architecture with security mechanism

Li, Chang,Qiao, Fei,Yang, Huazhong

ICETC 2010 - 2010 2nd International Conference on Education Technology and Computer, Published 2010, Volume 1, Pages V1573-V1577

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46.一种适用于H.264标准的高度并行双层流水线结构CAVLC编码器

乔飞,魏鼎力,杨华中,汪蕙

电子学报[0372-2112], Published 2010, Issue 07, Pages 235-240

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47.基于模块划分方法的MPEG-2解码芯片可测性设计

廖富成,乔飞,周妮,谭斯斯,杨华中

电视技术[1002-8692], Published 2010, Issue 11, Pages 37-41

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48.32位MIPS处理器可测性设计与实现

周妮,乔飞,谭斯斯,李常,杨华中

微电子学[1004-3365], Published 2010, Issue 06, Pages 20-24+29

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49.A functional model of SystemC-Based MPEG-2 decoder with heterogeneous Multi-IP-Cores and Hybrid-Interconnections architecture

Tan, Sisi,Qiao, Fei,Xia, Bingbing,Yang, Huazhong,Wang, Hui

PROCEEDINGS OF THE 2009 2ND INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOLS 1-9, Published 2009, Pages 3212-3216

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50.A programmable DCO-Based Fast-Locking clock generator

Qiao, Fei,Zhou, Yuan,Xie, Xiang,Yang, Huazhong

2009 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS 2009), Published 2009, Pages 93-98

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51.Low-standby-current and high-speed SAFF with improved conditional-precharge modules

Qiao, Fei,Yang, Huazhong,Wang, Hui

INTERNATIONAL JOURNAL OF ELECTRONICS[0020-7217], Published 2009, Volume 96, Issue 6, Pages 639-656

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52.Memory reduction techniques for HDTV video decoders

Gao, Hongli,Qiao, Fei,Yang, Huazhong,Wang, Hui

Recent Patents on Electrical Engineering[1874-4761], Published 2009, Volume 2, Issue 3, Pages 215-225

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53.HDTV解码中的无损存储压缩及高效帧存结构(英文)

高红莉,乔飞,杨华中

应用科学学报[0255-8297], Published 2009, Issue 01, Pages 71-77

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54.A lossless memory reduction and efficient frame storage architecture for HDTV video decoder

Gao, Hongli,Qiao, Fei,Yang, Huazhong

2008 INTERNATIONAL CONFERENCE ON AUDIO, LANGUAGE AND IMAGE PROCESSING, VOLS 1 AND 2, PROCEEDINGS, Published 2008, Pages 593-598

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55.SRAM-less deblocking filter in H.264/AVC

Li, Jian,Qiao, Fei,Luo, Rong,Yang, Hua-Zhong

Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology[1009-5896], Published 2008, Volume 30, Issue 8, Pages 2012-2016

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56.可用于高速片上系统异步IP互连的低摆幅差分接口电路

乔飞,杨华中,黄刚,汪蕙

中国科学(E辑:信息科学)[1006-9275], Published 2008, Issue 04, Pages 149-158

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57.无SRAM的H.264/AVC去块效应滤波器

李健,乔飞,罗嵘,杨华中

电子与信息学报[1009-5896], Published 2008, Issue 08, Pages 238-242

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58.面向SOC的可配置AHB接口组件

张頔,权进国,乔飞,罗嵘,杨华中

电子与信息学报[1009-5896], Published 2008, Issue 08, Pages 234-237

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59.Modified conditional-precharge sense-amplifier-based flip-flop with improved speed

Qiao, Fei,Yang, Huazhong,Wei, Dingli,Wang, Hui

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS[0218-1266], Published 2007, Volume 16, Issue 2, Pages 199-210

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60.Timing improvements of conditional-precharge sense-amplifier-based flip-flop

Qiao Fei,Yang Huazhong,Gao Hongli,Wang Hui

CHINESE JOURNAL OF ELECTRONICS[1022-4653], Published 2007, Volume 16, Issue 2, Pages 231-235

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61.A novel low-power and high-speed master-slave D flip-flop

Gao, Hongli,Qiao, Fei,Wei, Dingli,Yang, Huazhong

TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4[0886-1420], Published 2006, Pages 409-412

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62.Low power switched-capacitor circuits powered by AC-power supply

Qiao, Fei,Yang, Huazhong,Wang, Hui

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors[0253-4177], Published 2006, Volume 27, Issue 12, Pages 2203-2208

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63.采用交流电源供电的低功耗开关电容电路

乔飞,杨华中,汪蕙

半导体学报[0253-4177], Published 2006, Issue 12, Pages 139-144

收录情况： CNKI

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64.A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection

Yang, Huazhong,Qiao, Fei,Huang, Gang,Wang, Hui

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings, Published 2005, Volume 1, Pages 86-89

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65.宽工作电压范围单电源CMOS误差放大器

乔飞,杨华中,罗嵘,汪蕙

微电子学[1004-3365], Published 2004, Issue 01, Pages 85-87+90

收录情况： CNKI

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