姓 名：邓仰东
职 务：副教授
联系方式：**
邮 箱：dengyd@tsinghua.edu.cn

教育背景 1990-1995 清华大学电子工程系 学士
1995-1998 清华大学电子工程系 硕士
1998-2006 卡内基梅隆大学电子与计算机工程系 博士

工作履历 2004– 2006 高级软件工程师 Incentia Design Automation
2006 – 2008软件架构师 Magma Design Automation(Synopsys)
2008 – 2013 副研究员 清华大学微电子学研究所
2013 – 现在 博导、副研究员 清华大学软件学院

学术兼职 中车集团重大专项“轨道交通装备故障预测与健康管理技术研究与应用”项目副总设计师 2017 – 现在
NVIDIA合作教授2010 –现在
中国精品课程中心特邀课程专家暨“众核并行计算”课程主编 2010 –现在
International Workshop on Frontier of GPU Computing会议主席2012, 2011, 2010
VLSI Design Journal特邀主编Jan. 2012
Technical program committeeIEEE Computer Society Annual Symposium on VLSI (2013，2012，2011，2010，2009), HPC China (2013), ASP-DAC(2012),ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (2010), IEEE/ACM Great Lakes Symposium on VLSI (2010)
CUDA校园编程竞赛评委2013，2012，2011，2010，2009

研究领域 工业大数据：针对工业装备的状态监控、故障检测和剩余寿命预测方法
类脑计算：整合深度神经网络和贝叶斯推理的预测式学习方法和集成电路设计

研究概况 基于现代图形处理器的超大规模并行逻辑仿真Intel国际合作, 2012 – 2013
基于仿真的开源片上平台建模环境Intel国际合作, 2010 – 2011
基于Intel Ct技术的电子设计自动化算法研究Intel国际合作, 2010 – 2011
CUDA Excellence Center at Tsinghua UniversityNVIDIA国际合作项目，2010 – 现在
基于仿真的开源片上平台建模环境Intel国际合作, 2009 – 2011
轨道车辆嵌入式网络通信设备硬件子课题清华大学与北车集团联合科研项目, 2012
三维集成光线追踪图形处理器体系结构研究清华大学自主科研计划, 2012 – 2015
基于光线追踪机制的三维集成图形处理器体系结构研究中国国家自然科学基金, 2012 – 2016
基于多物理信号的高速列车系统级健康分析仪器中国国家自然科学基金重大仪器项目，2016 – 现在
轨道交通装备故障预测与健康管理技术研究与应用中国中车科研计划重大专项，2017 – 2019
产品服务生命周期集成平台研发国家重点研发计划，2019 – 现在

奖励与荣誉 清华大学骨干人才基金 2008年
NVIDIA合作教授奖 2010年，2009年
清华大学挑战杯优秀指导教师奖 2010年
国际计算机设计会议(International Conference on Computer Design)最佳论文奖 2013年
PASCAL VOC挑战赛目标检测第一名 2017年
MS Coco挑战赛目标检测第一名 2017年
计算机视觉和模式识别大会无人驾驶挑战赛目标检测第一名 2018年

学术成果 专著
1. Y. Deng, H. Chen, and Y. Liu, “Parallel Programming for Many-Core Processors,” Higher Education Publishing House, 2014.
2. Y. Deng and W. Maly, “3-D VLSI – A 2.5-D Integration Scheme,” Springer Verlag/Tsinghua University Publishing House, 2010.
3. Z. Wang and Y. Deng, “Structural VLSI Design and High Level Synthesis,” Tsinghua Publishing House, 1998. (清华大学集成电路设计课程教材)
特邀综述论文
1. Y. Deng and S. Mu, “A Survey on GPU Based Electronic Design Automation Computing,” Invited Paper, Foundation and Trends in Electronics Design Automation, Now Publishers, 2013, (单行本综述论文，180页).
2. Y. Deng, D. Wang, and Y. Zhu, “Asynchronous Parallel Logic Simulation on Modern Graphics Processors,” Why Scientists and Engineers Need GPUs, Springer, 2012.
3. Y. Deng, “Hardware/Software Co-Design for System-on-Chips,” Communications of China Computer Federation, Feb. 2012.
4. Y. Deng, "GPU Accelerated VLSI Design Verification," Invited paper, First International Workshop on Frontier of GPU Computing, Jun. 2010.
代表性会议论文
1. Zeming Li, Chao Peng, Gang Yu, Xiangyu Zhang, Yangdong Deng, Jian Sun, DetNet: A Backbone network for Object Detection, ECCV, 2018. (深度学习目标检测)
2. J. Huang, Y. Gao, S. Lu, X. Zhao, Y. Deng, and M. Gu, Energy-Efficient Automatic Train Driving by Learning Driving Patterns, AAAI, 2018. (人工智能节能驾驶)
3. Z. Li, Y. Chen, G. Yu, and Y. Deng, R-FCN++: Towards Accurate Region-based Fully Convolutional Networks for Object Detection, AAAI, 2018. (深度学习目标检测)
4. Z. Li, L. Liu, Y. Deng, S. Yin, Y. Wang, and S. Wei, Aggressive Parallelization of Irregular Applications on Reconfigurable Architectures, 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, 2017. (高性能计算机体系结构)
5. Z. Li, Y. Deng, and M. Gu: Path compression kd-trees with multi-layer parallel construction a case study on ray tracing. ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games (I3D), 2017. (高性能计算机体系结构)
6. X. Wang, Y. Deng, G. Zhang, and Z. Wang, Apparent resolution enhancement for near-eye light field display, SIGGRAPH Asia Mobile Graphics and Interactive Applications, 2015. (高性能AR设备)
7. Y. Wang, C. Liu, and Y. Deng, A feasibility study of ray tracing on mobile GPUs, SIGGRAPH Asia 2014 Mobile Graphics and Interactive Applications, 2014. (高性能计算机体系结构)
8. T. Wang and Y. Deng, Mining Effective Parallelism from Hidden Coherence for GPU Based Path Tracing, SIGGRAPH Asia, 2013. (高性能计算机体系结构)
9. K. Fang, Y. Ni, J. He, Z. Li, S. Mu, and Y. Deng, FastLane: An FPGA Accelerated GPU Microarchitecture Simulator, IEEE International Conference on Computer Design, 2013. (开源GPU处理器，最佳论文奖)
10.Y. Deng, B. Wang, and S. Mu, "Taming Irregular EDA Applications on GPUs," IEEE/ACM International Conference on Computer-Aided Design, Nov. 2009.(高性能计算)
代表性期刊论文
1. Y. Deng and S. Mu, “A Survey on GPU Based Electronic Design Automation Computing,” Invited Paper, Foundation and Trends in Electronics Design Automation, Now Publishers, 2013. (GPU计算综述)
2. S. Mu, Y. Deng, et. al. “Orchestrating Cache Management and Memory Scheduling for GPGPU Applications”, IEEE Transaction on Very Large Scale Integration, 2014.
3. Y. Jiang, H. Zhang, Z. Li, Y. Deng, X. Song, M. Gu, and J.-G. Sun: Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques. IEEE Trans. Industrial Electronics 62(2): 1270-1278 (2015). . (形式验证)
4. J. Huang, Y. Deng, Q. Yang, J. Sun, An Energy- Efficient Train Control Framework for Smart Railway Transportation: IEEE Transactions on Computers 65, no. 5 (2016): 1407-1417. (人工智能交通应用)
5. Y. Deng, Y. Ni, Z. Li, S. Mu S. and W. Zhang, Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques, ACM Computing Surveys, 2017.(光线追踪GPU体系结构)
6. Y. Lu, L. Liu, Leibo, Y. Deng, J. Weng, S. Yin, Y. Shi, S. Wei, Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays, IEEE Transactions on Parallel and Distributed Systems, 2018. (可重构计算机)
7. J. Huang, Q. Huang, Y.Deng, and Y.-H. Chen. “Toward Robust Vehicle Platooning With Bounded Spacing Error.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 4 (2017): 562-572. (人工智能交通应用)
8. Z. Li , L. Liu , Y. Deng, S.Yin , and S. Wei, Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution, IEEE Computer Architecture Letters, Vol.17, No. 2, July-Dec. 1 2018.(可重构计算机)
9. Y. Lu, L. Liu, Leibo, Y. Deng, J. Weng, S. Yin, Y. Shi, S. Wei, Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays, Accepted, IEEE, Transactions on Parallel and Distributed Systems. (可重构计算机)
10.Z.Li, H. Wang, Y. Deng, X. Zhao, Y. Gao, X. Song, and M. Gu. Time-triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018. (高性能硬件)