姓名：蔡懿慈
职称：教授
电话：**
邮箱：caiyc@mail.tsinghua.edu.cn
教育背景工学学士 (半导体物理与器件), 清华大学, 中国, 1983;
工学硕士 (计算机应用), 清华大学, 中国, 1986;
工学博士 (计算机应用), 中国科学技术大学, 中国, 2007.
学术兼职清华大学计算机系软件与理论研究所: 所长 (2008-);
清华大学计算机系分学术委员会: 委员 (2008-);
Integration, VLSI of Journal: 编委 (2009-2011);
《半导体学报》: 编委 (2009-2011).
研究领域集成电路计算机辅助设计软件，算法及软件系统
研究概况我的主要研究兴趣为微电子与计算机交叉领域中的IC设计优化算法与大规模数值计算分析，已经从事EDA领域研究工作20多年。近年来，伴随着Moore定律的发展，我对IC设计中的互连线时延和噪声分析优化、大规模IC供电网络并行分析、低功耗物理设计优化、以及纳米工艺下面向可制造性（DFM）设计优化等一些国际前沿性问题进行了深入的研究。先后参加或主持了国家“核高基”科技重大专项、973、863、国家自然科学基金重大国际合作、国家自然科学基金等多项国际科研或合作项目。 主要工作分为以下三方面：
1. 对IC片上供电网络的分析和优化进行了系统和深入的研究：提出了基于GPU的P/G网络并行分析快速泊松方法，获得DAC 2009最佳论文提名奖，这是大陆首次获得该项荣誉；提出了基于三维模型的大规模P/G网络快速分析方法，成果发表在国际IC物理设计年会ISPD 2006及国际期刊Trans. On CAD上；提出了Dcap电容优化与布局结合等一系列P/G网络优化方法，成果发表在国际会议ICCAD 2009及国际期刊Trans. On CAS-II国际期刊上。
2. 对IC低功耗与时序物理设计优化进行了研究：提出了性能驱动的功耗关断物理优化方法，获得以功耗优化为主题的国际年会SGLVLSI 2008最佳论文奖，这是大陆首次获得该项荣誉；提出了基于电压岛多供电功耗优化方法、时钟关断功耗优化方法等，成果发表在国际IC物理设计年会ISPD 2008及国际期刊Trans. On VLSI上。
3. 对纳米工艺下工艺参数变化及可制造性（DFM）问题进行深入研究：与Synopsys合作提出了基于区域模型匹配的OPC热点探测方法，获得ICCAD 2006最佳论文提名奖；提出了一系列面向DFM的布线和优化算法，成果发表在国际会议及Trans. On VLSI等国际期刊上。
研究课题
国家“核高基”科技重大专项: 先进EDA工具平台开发 (2008-2010);
国家自然科学基金海外青年合作: 考虑工艺参数变化的IC设计优化理论与关键技术 (2009-2010);
国家自然科学基金: 极大规模集成电路片上供电网络仿真及优化 (2008-2010);
国家自然科学基金: 纳米工艺下集成电路自动布线算法研究 (2010-2012).
奖励与荣誉教育部科技进步二等奖——超大规模集成电路物理级优化和验证问题基础研究 (2006);
DAC 2009: 最佳论文提名奖 (2009);
ICCAD2006: 最佳论文提名奖 (2006);
GLVLSI 2008: 最佳论文奖 (2008);
清华大学: 教学优秀奖 (2000).
学术成果[1] J. Shi, Y. C. Cai, W. T. Hou, L. W. Ma, S. X.-D. Tan, P-H. Ho, X. Y. Wang, GPU friendly Fast Poisson Solver for Structured Power Grid Network Analysis, in Proc. Design Automation Conference (DAC 2009), San Francisco, USA, July 2009, PP.178-183. (Best Paper Nomination)
[2] J. Shi, Y. C. Cai, S. X.-D. Tan, X. L. Hong, High Accurate Pattern Based Precondition Method for Extremely Large Power/Ground Grid Analysis, in Prof. International Symposium on Physical Design (ISPD 2006), San Jose, USA, April 2006, PP.108-113.
[3] J. Shi, Y. C. Cai, S. X.-D. Tan, J. Fan, X. L. Hong, Pattern Based Iterative Method for Extreme Large Power/Ground Analysis, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems（TCAD）, Vol.26, No.4, PP. 680-692, 2007.
[4] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, Decoupling Capacitance Budgeting Aware Placement For Transient Power Supply Noise Elimination, in Proc. Integrated Circuit Computer Aided Design (ICCAD 2009), San Jose, USA, Nov. 2009, PP. 745-751.
[5] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, X. L. Hong, J. Relles, An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models. in Proc. ACM/IEEE Design, Automation & Test in Europe Conference (DATE 2009), Nice, France, April 2009, PP.1190–1195.
[6] Y. C. Cai, L. Kang, J. Shi, X. L. Hong, S. X.-D. Tan, Random Walk Based Optimization Approach for Power/Ground Network, IEEE Trans. on Circuits and Systems II(TCAS-II), Vol. 55, No. 1, PP. 36-40, 2008.
[7] Cai Yici, Fu Jingjing, Hong Xianlong, S. X._D. Tan and Z. Lou Power/Ground Network Optimization Considering Decap Leakage Currents, IEEE Trans. On Circuit and System (TCAS-II), Vol.53, No. 10, pp1012-1016, 2006.
[8] Guo Liangpeng, Cai Yici, Zhou Qiang, Hong Xianlong, Performance Driven Power Gating Based on Distributed Sleep Transistor Network, Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (SGLVLSI 2008), Orlando, Florida, USA, May 2008, pp255-260. (Best Paper Award)
[9] Y. C. Cai, B. Liu, Q. Zhou, X. L. Hong, Voltage Island Generation in Cell Based Dual-Vdd Design, IEICE Trans. Fundamentals of Electronic, Communications and Computer Science, Vol. E90-A, No.1, PP.267-273, 2007.
[10] W. X. Shen, Y. C. Cai, X. L. Hong, Activity and Register placement Aware Gated Clock Tree Design, in Prof. International Symposium on Physical Design (ISPD 2008), Portland, Oregon, USA, 2008, PP.182-189.
[11] Shen Weixiang, Cai Yici, Hong Xianlong, An Effective Gated Clock Network Design Based on Activity and Register Aware Placement, IEEE Trans. on Very Large Scale Integration Systems (TVLSI), (to appear).
[12] H. Yao, S. Sinha, C. Chiang, X. Hong and Y. Cai, "Efficient Process-hotspot Detection Using Range Pattern Matching," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), San Jose, USA, Nov. 2006, pp. 625-632. (Best Paper Nomination)
[13] H. Yao, S. Sinha, J. Xu, C. Chiang, Y. Cai and X. Hong, "Efficient range pattern matching algorithm for process-hotspot detection," IET Circuits, Devices & Systems, Vol.2, No. 1, pp. 2-15, 2008.
[14] Y. Shen, Q. Zhou, Y. C. Cai, X. L. Hong, ECP and CMP Aware Detailed Routing Algorithms for DFM, IEEE Trans. On Very Large Scale Integration Systems (TVLSI), Vol.18, No. 1, PP.153-157, 2010.
[15] X. Hong, Y. Cai, H. Yao and D. Li, "DFM-aware Routing for Yield Enhancement," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 2006, pp. 1093-1096. (Invited paper)
[16] Jia Yanming, Cai Yici, Hong Xianlong, Dummy Fill Aware Buffer Insertion After Layer Assignment Based On An Effective Estimation Model, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E91-A, No.12, 2008, pp.3783-3792.
[17] 蔡懿慈, 周强. 超大规模集集成电路设计导论. 清华大学出版社, 北京, 2005.