刘勇攀 博士 教授
电路与系统所 所长

中国北京市清华大学电子工程系 100084
电话： +86-
传真：+86-
电子邮箱： ypliu@tsinghua.edu.cn
个人网页：http://nics.ee.tsinghua.edu.cn/people/liuyp/


围绕后摩尔时代新型器件与人工智能应用带来的挑战与机遇，开展高能效电路与系统研究。1）针对基于新型存储器件的计算理论与架构缺失，提出了自供能电路理论和存算融合的非易失计算架构，发明了非易失处理器THU10XN系列芯片，突破了传统CMOS计算芯片能效与计算模式的瓶颈；2）针对新兴深度学习应用对算力快速提升的挑战，提出领域专用智能算芯一体的协同理论与系统架构，发明了多维度稀疏自适应智能计算架构和系列芯片，突破了传统智能芯片能效与优化维度局限；3）针对智能制造等重大需求，提出了基于智能边缘计算芯片的物联网感知、调度与端边云协同优化技术，转移至湃方科技和源清慧虹等创业公司进行产业化。
担任国家自然科学基金会评专家和创新特区项目论证专家，主持自然科学基金重点，国家重点研发计划，创新特区等重点项目10余项。曾获教育部技术发明一等奖，中国公路学会科学技术一等奖和电子学会科学技术二等奖。近年发表JSSC/TCAD/TCAS等 IEEE/ACM Trans论文35篇，ISSCC/DAC/VLSI在内会议论文85篇。2017年入选国际电子设计自动化领域DAC under 40岁以下发明创新奖，ASP-DAC 2017最佳论文，IEEE Micro Top Pick 2016，HPCA2015最佳论文以及低功耗电子系统设计竞赛奖ISLPED2012,2013和2019，2019纽伦堡发明展银奖等。担任IEEE TCAD/TCAS-II，IET CPS编委，ASPDAC 2020设计自动化会议秘书长，NVMSA 2019非易失存储会议技术委员会主席，IWCR2018跨层可靠性会议主席，AWSSS2016智能传感会议主席，A-SSCC2019智能芯片Panelist和DAC, DATE, ASPDAC, ISLPED，A-SSCC技术委员。

教育背景2004-2007年， 清华大学电子工程系，博士
1995-2002年， 清华大学电子工程系，本硕连读


工作履历2020-至今， 清华大学电子工程系，长聘教授
2017-2019年， 清华大学电子工程系，长聘副教授，研究员
2017年4-6月，香港城市大学计算机科学系，访问
2014年7-9月，美国宾夕法尼亚州立大学计算机科学系，访问
2007-2016年， 清华大学电子工程系，助理研究员和副研究员
2004-2007年， 清华大学电子工程系，博士
2002-2004年， 清华大学电子工程系，助研



研究领域1、 专用领域人工智能芯片及架构，包括感算一体、目标检测、视频压缩和自动驾驶
2、 基于新型器件的计算存储芯片及架构，包括存算一体、非易失处理器和自供能电路
3、 智能物联网电路与系统，包括功耗模型与评估、大面积感知系统和边缘智能物联网

研究概况1、 新原理存储器件的存内计算关键技术研究，国家自然科学基金重点项目，2020-2025，项目负责人
2、 存算一体器件及其计算新架构，国家重点研发计划，2019-2024，课题负责人
3、 智能芯片IP，特区重点项目，2019-2020，课题负责人
4、 智能数据存储，主题重点项目，2019-2021，项目负责人
5、 CMOS无线体域网收发器芯片技术，预研重点项目，2017-2020，项目负责人


学术成果[1] Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm Computing-in-Memory Based CNN Processor with 2.9-35.8TOP/W System Energy Efficiency Using Dynamic Sparsity Performance Scaling Architecture and Energy Efficient Inter/Intra Macro Data Reuse, IEEE International Solid-state Circuits Conference (ISSCC), Accepted, 2020.
[2] Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu,Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm 24.7 uJ/Frame 12.3 mW Activation Similarity Aware Convolutional Neural Network Video Processor Using Hybrid Precision Inter Frame Data Reuse and Mixed-Bit-Width Difference Frame Data Codec," IEEE International Solid-state Circuits Conference (ISSCC), Accepted, 2020.
[3] Yongpan Liu*, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, , Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, and Huazhong Yang, A 130-nm Ferroelectric Nonvolatile System-On-Chip with Direct Peripheral Restore Architecture for Transient Computing System，IEEE Journal of Solid-State Circuits (JSSC), 2019, 54(3): 885 - 895
[4] Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural- Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1× Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture, IEEE International Solid-state Circuits Conference (ISSCC), pp. 138-140.
[5] Zhe Yuan, Yongpan Liu*, Jinshan Yue, Yixiong Yang, Jingyu Wang, Xiaoyu Feng, Xueqing Li Huazhong Yang, STICKER: An Energy Efficient Multi-Sparsity Compatible Accelerator for Deep Convolutional Neural Networks in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), Early Access, 2019: 1-13
[6] J Wu, H Zhong, K Ni, Yongpan Liu, H Yang, X Li, “A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs”, Proceedings of the 56th Annual Design Automation Conference (DAC), 2019.
[7] Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, “STICKER: A 0.41-62.1 TOPS/W 8bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers”, VLSI Circuits (VLSI), 2018 Symposium on. 2018: 33-34
[8] Patrick Cronin, Chengmo Yang, Yongpan Liu, “A collaborative defense against wear out attacks in non-volatile processors”, Design Automation Conference (DAC), 2018: 88:1-88:6.
[9] Zhibo Wang, Yongpan Liu*, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, and Huazhong Yang, A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving >4x Faster Clock Frequency and >6x Higher Restore Speed”, IEEE Journal of Solid-State Circuits (JSSC), 2017, 52(10): 2769-2785.
[10] Fang Su, Wei-Hao Chen, Lixue Xia, Chieh-Pu Lo, Tianqi Tang, Zhibo Wang, Kuo-Hsiang Hsu, Ming Cheng, Jun-Yi Li, Yuan Xie, Yu Wang, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory”, VLSI Circuits (VLSI), 2017 Symposium on. IEEE, 2017: C260-C261.
[11] Zhibo Wang, Fang Su, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Meng-Fan Chang, Huazhong Yang, Yongpan Liu*, “A 130nm FeRAM-Based Parallel Recovery Nonvolatile SOC for Normally-OFF Operations with 3.9× Faster Running Speed and 11× Higher Energy Efficiency Using Fast Power-On Detection and Nonvolatile Radio Controller”, VLSI Circuits (VLSI), 2017 Symposium on. IEEE, 2017: C336-C337.
[12] Su Fang, Yongpan Liu*, Yiqun Wang, Huazhong Yang, “A Ferroelectric Nonvolatile Processor with 46 μs System-Level Wake-up Time and 14 μs Sleep Time for Energy Harvesting Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2017, 64(3): 596-607.
[13] Yongpan Liu*; Zhibo Wang; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei; Yu Wang; Ya-Chin King; Chrong-Jung Lin; Pedram Khalili; Kang-Lung Wang; Meng-Fan Chang; Huazhong Yang, “A 65nm ReRAM-Enabled Nonvolatile Processor with 6x Reduction in Restore Time and 4x Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logics”, IEEE International Solid-state Circuits Conference (ISSCC), 2016, pp. 84-86.
[14] Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang and Yuan Xie, “PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory” ,43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), 2016, pp.1-13.
[15] Yongpan Liu*, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, Sampson John,Yuan Xie, Jiwu Shu, and Huazhong Yang, “Ambient Energy Harvesting Nonvolatile Processors: From Circuit to System”, Proceedings of the Design Automation Conference (DAC), 2015, pp.1-6.
[16] 刘勇攀，袁哲，岳金山，杨华中等，一种应用于卷积神经网络的处理器，（专利入股湃方科技），5.1
[17] 龙衡宇，刘勇攀，杨华中，一种能量分配的方法和装置，（专利入股源清慧虹），5.8
[18] 龙衡宇，刘勇攀，应蓓华，杨华中，一种自适应划分簇的方法及系统，（专利入股源清慧虹），7. 7