Author(s): Ma, S (Ma, Song); Liu, LY (Liu, Liyuan); Fang, T (Fang, Tong); Liu, J (Liu, Jian); Wu, NJ (Wu, Nanjian)
Source: IEEE JOURNAL OF SOLID-STATE CIRCUITS Volume: 55 Issue: 2 Pages: 333-343 DOI: 10.1109/JSSC.2019.2941540 Published: FEB 2020
Abstract: This article presents a discrete-time second-order $\Delta \Sigma $ modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm(2) core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49- $\mu \text{W}$ power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.
Accession Number: WOS:000510725300010
ISSN: 0018-9200
eISSN: 1558-173X
Full Test: https://ieeexplore.ieee.org/document/8862953/