北京航空航天大学导师教师信息介绍简介-成元庆

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个人简历

2012年博士毕业于中国科学院计算技术研究所，导师，李晓维研究员。2012-2013在法国CNRS-LIRMM实验室做博士后研究，导师Patrick Girard研究员和Aida Todri-Sanial研究员。2013年底加入北京航空航天大学。2015-2016年在美国加州大学圣芭芭拉分校谢源教授课题组做学术访问。
目前为CCF高级会员，计算机体系结构专委委员，ACM/IEEE/IEICE会员，欧洲集成电路设计自动化与测试会议程序委员会委员，欧洲PATMOS会议程序委员会委员，IEEE Trans. on CAD, IEEE Trans. on VLSI, Elsivier Integration Jounal, Elsivier Microelectronics Jounal特约审稿人。
承担过国家自然科学基金青年基金1项，北京市自然科学基金青年项目1项，北航“蓝天新秀”专项基金1项。在研北京市自然科学基金面上项目1项，计算机体系结构国家重点实验室开放课题1项，航天二院航天科学基金1项。
参与编纂英文学术专著1部，发表包括ICCAD, IEEE Trans. on CAD, IEEE Trans. on VLSI等在内40余篇学术论文。荣获2017年北京市科学技术二等奖1项。
实验室主页：www.cadetlab.cn

教育经历

[1] 中国科学院计算技术研究所博士学位 | 博士研究生毕业
[2] 哈尔滨工业大学 Master's Degree | 硕士研究生毕业
[3] 西安电子科技大学 Bachelor's Degree | 大学本科毕业

工作经历

[1] 美国加州大学圣芭芭拉分校 |访问学者

[2] 北京航空航天大学 |微电子学院

[3] 法国CNRS-LIRMM |微电子 |博士后

社会兼职

[1]2017.3-至今
PATMOS会议 TPC
[2]2018.3-2022.3
DATE TPC委员
[3]2019.3-至今
IEICE会员
[4]2013.3-至今
IEEE会员
[5]2012.3-至今
ACM会员
[6]2018.3-至今
CCF体系结构专委委员
[7]2016.3-至今
CCF高级会员

研究方向

[1] 基于新型半导体器件的低功耗设计技术

[2] 三维集成电路体系结构设计及设计自动化技术

团队成员

CADET
Computer Architecture/Aided Design for Emerging Technologies

倪嘉诚 研究生一年级，单体三维集成电路高性能体系结构设计

王璇研究生一年级，数字集成电路芯片设计

王微研究生一年级，单体三维集成电路物理设计技术

陈琳研究生二年级，碳纳米管存储器低功耗设计研究

张亮研究生二年级，数字集成电路芯片设计

研究领域

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三维集成电路体系结构设计和设计自动化技术
基于新型半导体器件的低功耗计算机体系结构研究

开授课程

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[1]微机原理与接口技术

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科研项目

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[1] 基于STT-MRAM的存储计算架构设计研究
[2] 北京航空航天大学“蓝天新秀”人才专项, 已结题
[3] 基于自旋转移矩磁性存储器的片上高速缓存可靠性设计方法研究, 已结题
[4] 基于STT-MRAM的三维片上多核系统缓存低功耗设计方法研究, 已结题

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论文

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[1] [c1] Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu and Xiaowei Li, "Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC", in Proceedings of IEEE Asian Test Symposium (ATS), New Delhi, India, Nov. 2011, pp. 181-186.
[2] [c2] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet and Marc Belleville, "A novel method to mitigate TSV electromigration for 3D ICs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Natal, Brazil, Jul. 2013, pp. 121-126.
[3] [j1] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), vol. 28, no. 1, pp. 119-128, 2013.
[4] [j2] Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 21, no. 2, pp. 239-249, 2013.
[5] [c3] Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, and Arnaud Virazel, "Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Jan. 2014, pp.544-549.
[6] [c4] Xiaolong Zhang, Yuanqing Cheng*, Weisheng Zhao, Youguang Zhang and Aida Todri-Sanial, "Exploring Potentials of Perpendicular Magnetic Anisotropy STT-MRAM for Cache Design", in Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 2014, pp. 893-895.
[7] [c5] Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng and Xiaowei Li, "HARS: A High-Performance Reliable Routing Scheme for 3D NoCs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, Jul. 2014, pp. 392-397.
[8] [c6] Lun Yang, Yuanqing Cheng*, Ying Wang, Hao Yu, Weisheng Zhao and Aida Todri-Sanial, "A body-biasing of readout circuit for STT-RAM with improved thermal reliability", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1530-1533.
[9] [c7] Xiaolong Zhang, Yuanqing Cheng*, Ying Wang, Weisheng Zhao and Aida Todri-Sanial, "Write back energy optimization for STT-RAM based cache using data pattern characterization", IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2015.
[10] [c8] Bi Wu, Yuanqing Cheng*, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao, "An architecture-level cache simulation framework supporting advanced PMA STT-MRAM", in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, MA, USA, Jul. 2015, pp. 7-12.
[11] [c9] Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein and Weisheng Zhao, "Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM", in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, Jul. 2015, pp. 461-466.
[12] [c10] Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li and Xiaowei Li, "A case of precision-tunable STT-RAM memory design for approximate neural network", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1534-1537.
[13] [j3] Yuanqing Cheng*, Aida Todri-Sanial, Jianlei Yang and Weisheng Zhao, "Alleviating Through Silicon Via Electromigration for Three-dimensional Integrated Circuits Taking Advantage of Self-healing Effect", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3310-3322, 2016.
[14] [c11] Ping Chi, Shuangchen Li, Yuanqing Cheng, Yv Lu, S. H. Kang and Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 2016, pp.109-114.
[15] [j4] Aida Todri-Sanial and Yuanqing Cheng, "A Study of 3-D Power Delivery Networks With Multiple Clock Domains", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3218-3231, 2016.
[16] [c12] Linuo Xue, Yuanqing Cheng*, Jianlei Yang, Peiyuan Wang and Yuan Xie, "ODESY: A novel 3T-3MTJ cell design with Optimized area DEnsity, Scalability and latency", in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Austin, TX, USA, Nov. 2016, pp. 1-8.
[17] "Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM", IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1755-1768, 2016.
[18] [j5] Bi Wu, Yuanqing Cheng*, Jianlei Yang, Aida Todri-Sanial and Weisheng Zhao,
[19] [c13] Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi and Mark Tehranipoor, "AES design improvement towards information safety", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1706-1709.
[20] [c14] Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng* and Weisheng Zhao, "Quantitative evaluation of reliability and performance for STT-MRAM", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1150-1153.

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荣誉及奖励

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[1]北京市科技进步奖二等奖

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